Wesley W. Terpstra 93b2fa197e Artefact output (#545) ...

* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts

2017-02-02 19:24:55 -08:00

..

.gitignore

Write test harness in Chisel

2016-08-15 23:27:27 -07:00

Makefile

Use PROJECT rather than MODEL in name of binary and generated src files.

2016-09-19 13:23:17 -07:00

Makefrag

Artefact output (#545)

2017-02-02 19:24:55 -08:00

Makefrag-verilog

Artefact output (#545)

2017-02-02 19:24:55 -08:00

vlsi_mem_gen

Perform integer division when parsing rocketchip.DefaultConfig.conf (#493)

2017-01-13 16:40:02 -08:00