riscv/rocket-chip
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Remove ClockToSignal and vice-versa

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Clock.asUInt and Bool.asClock now suffice.
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Andrew Waterman committed 2016-09-21 16:17:14 -07:00
1 parent 2ab61f1a71
commit 8e63f4a1a5
4 files changed
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vsim/Makefrag
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@@ -10,8 +10,6 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
$(base_dir)/vsrc/AsyncResetReg.v \
$(base_dir)/vsrc/AsyncSetReg.v \
$(base_dir)/vsrc/ClockDivider.v \
$(base_dir)/vsrc/ClockToSignal.v \
$(base_dir)/vsrc/SignalToClock.v \
sim_vsrcs = \