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Use vlsi_mem_gen for verilator flow

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This commit is contained in:
Andrew Waterman
2017-08-07 20:36:22 -07:00
parent b0f32c8f09
commit ea4b1bc349
3 changed files with 15 additions and 6 deletions
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vsim/Makefile
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@ -11,7 +11,6 @@ default: all
base_dir = $(abspath ..)
generated_dir = $(abspath ./generated-src)
VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
mem_gen = $(VLSI_MEM_GEN)
sim_dir = .
output_dir = $(sim_dir)/output