riscv/rocket-chip
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debug: remove old Verilog DebugTransportModuleJtag file as it has been replaced by Chisel version

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This commit is contained in:
Megan Wachs
2017-03-27 21:24:44 -07:00
parent bb64c92906
commit cbc8d2400a
2 changed files with 1 additions and 338 deletions
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vsim/Makefrag
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@ -4,7 +4,7 @@
# Verilog sources
bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
bb_vsrcs = \
$(base_dir)/vsrc/jtag_vpi.v \
$(base_dir)/vsrc/ClockDivider2.v \
$(base_dir)/vsrc/AsyncResetReg.v \