riscv/rocket-chip
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Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages.

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This commit is contained in:
Henry Cook 2016-09-22 15:59:29 -07:00
parent 83c08a931d
commit 411ee378de
9 changed files with 10 additions and 25 deletions
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2
Makefrag
View File

@ -23,8 +23,6 @@ $(FIRRTL_JAR): $(shell find $(base_dir)/firrtl/src/main/scala -iname "*.scala")
$(MAKE) -C $(base_dir)/firrtl SBT="$(SBT)" root_dir=$(base_dir)/firrtl build-scala
touch $(FIRRTL_JAR)
CHISEL_ARGS := --targetDir $(generated_dir)
src_path = src/main/scala
default_submodules = . hardfloat context-dependent-environments chisel3
chisel_srcs = $(foreach submodule,$(default_submodules) $(ROCKETCHIP_ADDONS),$(shell find $(base_dir)/$(submodule)/$(src_path) -name "*.scala"))

5
emulator/Makefile
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@ -23,10 +23,7 @@ debug: $(emu_debug)
clean:
rm -rf *.o *.a emulator-* $(generated_dir) $(generated_dir_debug) DVEfiles $(output_dir)
test:
cd $(base_dir) && $(SBT) "~make $(CURDIR) run-fast $(CHISEL_ARGS)"
.PHONY: default all debug clean test
.PHONY: default all debug clean
#--------------------------------------------------------------------
# Run assembly tests and benchmarks

4
emulator/Makefrag-verilator
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@ -10,11 +10,11 @@ verilog_debug = $(generated_dir_debug)/$(long_name).v
$(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(generated_dir_debug)/%.fir $(generated_dir_debug)/%.prm $(generated_dir_debug)/%.d: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(generated_dir_debug) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir_debug) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
%.v: %.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)

2
project/build.scala
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@ -32,7 +32,7 @@ object BuildSettings extends Build {
a.split(" ")
},
unmanagedSourceDirectories in Compile ++= addons.value.map(baseDirectory.value / _ / "src/main/scala"),
mainClass in (Compile, run) := Some("rocketchip.RocketChipGenerator"),
mainClass in (Compile, run) := Some("rocketchip.Generator"),
make := {
val jobs = java.lang.Runtime.getRuntime.availableProcessors
val (makeDir, target) = setMake.parsed

6
src/main/scala/groundtest/Generator.scala
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@ -2,11 +2,7 @@
package groundtest
import Chisel._
import util.Generator
object GroundtestGenerator extends Generator
{
object Generator extends util.GeneratorApp {
val longName = names.topModuleProject + "." + names.configs
generateFirrtl
generateTestSuiteMakefrags // TODO: Needed only for legacy make targets

6
src/main/scala/rocketchip/Generator.scala
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@ -2,14 +2,12 @@
package rocketchip
import Chisel._
import rocket.{XLen, UseVM, UseAtomics, UseCompressed, FPUKey}
import util.Generator
import scala.collection.mutable.LinkedHashSet
/** A Generator for platforms containing Rocket Coreplexes */
object RocketChipGenerator extends Generator
{
object Generator extends util.GeneratorApp {
val rv64RegrTestNames = LinkedHashSet(
"rv64ud-v-fcvt",
"rv64ud-p-fdiv",

6
src/main/scala/unittest/Generator.scala
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@ -2,11 +2,7 @@
package unittest
import Chisel._
import util.Generator
object UnitTestGenerator extends Generator
{
object Generator extends util.GeneratorApp {
val longName = names.topModuleProject + "." + names.configs
generateFirrtl
generateTestSuiteMakefrags // TODO: Needed only for legacy make targets

2
src/main/scala/util/GeneratorUtils.scala
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@ -60,7 +60,7 @@ trait HasGeneratorUtilities {
/** Standardized command line interface for Scala entry point */
trait Generator extends App with HasGeneratorUtilities {
trait GeneratorApp extends App with HasGeneratorUtilities {
lazy val names: ParsedInputNames = {
require(args.size == 5, "Usage: sbt> " +
"run TargetDir TopModuleProjectName TopModuleName " +

2
vsim/Makefrag-verilog
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@ -10,7 +10,7 @@ verilog = $(generated_dir)/$(long_name).v
$(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(generated_dir)/$(long_name).v $(generated_dir)/$(long_name).conf : $(firrtl) $(FIRRTL_JAR)
mkdir -p $(dir $@)