Howard MaoandAndrew Waterman a19bd6de96 Get in line with FIRRTL randomization flag changes (#231)

2016-08-29 12:29:01 -07:00

..

.gitignore

Write test harness in Chisel

2016-08-15 23:27:27 -07:00

Makefile

More accurate conditional include of generated .d make fragment (#222)

2016-08-25 14:42:04 -07:00

Makefrag

Get in line with FIRRTL randomization flag changes (#231)

2016-08-29 12:29:01 -07:00

Makefrag-verilog

Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227)

2016-08-25 17:26:28 -07:00

vlsi_mem_gen

Massive update containing several months of changes from the now-defunct private chip repo.

2015-07-02 14:43:30 -07:00