Use vlsi_mem_gen for verilator flow
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parent
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2
Makefrag
2
Makefrag
@ -10,6 +10,8 @@ CONFIG ?= DefaultConfig
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# TODO: For now must match rocketchip.Generator
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long_name = $(PROJECT).$(CONFIG)
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VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
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CXX ?= g++
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CXXFLAGS := -O1
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JVM_MEMORY ?= 2G
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@ -2,7 +2,9 @@
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# Verilator Generation
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#--------------------------------------------------------------------
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firrtl = $(generated_dir)/$(long_name).fir
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verilog = $(generated_dir)/$(long_name).v
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verilog = \
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$(generated_dir)/$(long_name).v \
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$(generated_dir)/$(long_name).behav_srams.v \
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.SECONDARY: $(firrtl) $(verilog)
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@ -10,9 +12,14 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
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%.v: %.fir $(FIRRTL_JAR)
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%.v %.conf: %.fir $(FIRRTL_JAR)
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mkdir -p $(dir $@)
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$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog
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$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf
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$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(VLSI_MEM_GEN)
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cd $(generated_dir) && \
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$(VLSI_MEM_GEN) $(generated_dir)/$(long_name).conf > $@.tmp && \
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mv -f $@.tmp $@
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# Build and install our own Verilator, to work around versionining issues.
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VERILATOR_VERSION=3.904
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@ -47,6 +54,7 @@ verilator: $(INSTALLED_VERILATOR)
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VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
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VERILATOR_FLAGS := --top-module $(MODEL) \
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+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
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--output-split 20000 \
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--output-split-cfuncs 20000 \
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@ -62,13 +70,13 @@ model_header_debug = $(generated_dir_debug)/$(long_name)/V$(MODEL).h
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$(emu): $(verilog) $(cppfiles) $(headers) $(INSTALLED_VERILATOR)
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mkdir -p $(generated_dir)/$(long_name)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(long_name) \
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-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
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-o $(abspath $(sim_dir))/$@ $(verilog) $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "-I$(generated_dir) -include $(model_header)"
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$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir)/$(long_name) -f V$(MODEL).mk
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$(emu_debug): $(verilog) $(cppfiles) $(headers) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
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mkdir -p $(generated_dir_debug)/$(long_name)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name) --trace \
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-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
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-o $(abspath $(sim_dir))/$@ $(verilog) $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug)"
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$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir_debug)/$(long_name) -f V$(MODEL).mk
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@ -11,7 +11,6 @@ default: all
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base_dir = $(abspath ..)
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generated_dir = $(abspath ./generated-src)
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VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
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mem_gen = $(VLSI_MEM_GEN)
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sim_dir = .
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output_dir = $(sim_dir)/output
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