riscv/rocket-chip
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Bump chisel3 and firrtl and bump sbt to version 1.0.4

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sbt bump must be accompanied by bump to chisel3 and firrtl using sbt
1.0.4
This commit is contained in:
Jack Koenig 2017-12-12 18:46:51 -08:00
parent b914564a62
commit 3df401eef7
7 changed files with 12 additions and 9 deletions
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9
build.sbt
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@ -2,7 +2,10 @@
import sbt.complete._
import sbt.complete.DefaultParsers._
import xerial.sbt.Pack._
import xerial.sbt.pack._
import sys.process._
enablePlugins(PackPlugin)
lazy val commonSettings = Seq(
organization := "berkeley",
@ -26,7 +29,7 @@ lazy val addons = settingKey[Seq[String]]("list of addons used for this build")
lazy val make = inputKey[Unit]("trigger backend-specific makefile command")
val setMake = NotSpace ~ ( Space ~> NotSpace )
val chipSettings = packAutoSettings ++ Seq(
val chipSettings = Seq(
addons := {
val a = sys.env.getOrElse("ROCKETCHIP_ADDONS", "")
println(s"Using addons: $a")
@ -38,6 +41,6 @@ val chipSettings = packAutoSettings ++ Seq(
val jobs = java.lang.Runtime.getRuntime.availableProcessors
val (makeDir, target) = setMake.parsed
(run in Compile).evaluated
s"make -C $makeDir -j $jobs $target" !
s"make -C $makeDir -j $jobs $target".!
}
)

2
chisel3

@ -1 +1 @@
Subproject commit 30e8eb552a29b22bc23faa06f5661da6129188b2
Subproject commit 9f504b9926d38d11fb8003c72360ff11d24b5ef6

2
emulator/Makefrag-verilator
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@ -10,7 +10,7 @@ verilog = \
$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
%.v %.conf: %.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)

2
firrtl

@ -1 +1 @@
Subproject commit 40dda493a277f721306d428ee967dcb670813275
Subproject commit 8ab501e7527139a4ee8d0b38f9b4384551387043

2
project/build.properties
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@ -1 +1 @@
sbt.version=0.13.16
sbt.version=1.0.4

2
project/plugins.sbt
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@ -6,7 +6,7 @@ addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1")
addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0")
addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.8.0")
addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3")
addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1")

2
vsim/Makefrag-verilog
View File

@ -10,7 +10,7 @@ verilog = $(generated_dir)/$(long_name).v
$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)