riscv/rocket-chip
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mem_gen failure doesn't create the target

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This commit is contained in:
Megan Wachs 2016-08-24 12:52:24 -07:00
parent 48098f5e2d
commit e95fe646a3
1 changed files with 4 additions and 2 deletions
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6
vsim/Makefrag-verilog
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@ -13,9 +13,11 @@ $(generated_dir)/%.v $(generated_dir)/%.conf : $(generated_dir)/%.fir $(FIRRTL_J
mkdir -p $(dir $@)
$(FIRRTL) -i $< -o $@ -X verilog --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(MODEL).$(CONFIG).conf
$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v : $(generated_dir)/$(MODEL).$(CONFIG).v $(generated_dir)/$(MODEL).$(CONFIG).conf $(mem_gen)
$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v : $(generated_dir)/$(MODEL).$(CONFIG).conf $(mem_gen)
cd $(generated_dir) && \
$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $@
rm -f $@ && \
$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $@.tmp && \
mv $@.tmp $@
$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm
echo "\`ifndef CONST_VH" > $@