riscv/rocket-chip
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Bump chisel3 and firrtl and bump sbt to version 1.0.4

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sbt bump must be accompanied by bump to chisel3 and firrtl using sbt
1.0.4
This commit is contained in:
Jack Koenig
2017-12-12 18:46:51 -08:00
parent b914564a62
commit 3df401eef7
7 changed files with 12 additions and 9 deletions
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2
vsim/Makefrag-verilog
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@ -10,7 +10,7 @@ verilog = $(generated_dir)/$(long_name).v
$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)