riscv/rocket-chip
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Bump firrtl and update vsim Makefrag-verilog (#409)

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Jack Koenig 2016-10-23 23:07:47 -07:00 committed by Andrew Waterman
parent 8bfd6bcd4d
commit 288d7169ae
2 changed files with 2 additions and 2 deletions
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2
firrtl

@ -1 +1 @@
Subproject commit 8b12dcbb76896a19f95dc4da19b3b8c74c1ddda3
Subproject commit bcf73fb70969e5629a693c18f1f2ee7b37f14a76

2
vsim/Makefrag-verilog
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@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_src
$(generated_dir)/$(long_name).v $(generated_dir)/$(long_name).conf : $(firrtl) $(FIRRTL_JAR)
mkdir -p $(dir $@)
$(FIRRTL) -i $< -o $(generated_dir)/$(long_name).v -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
$(FIRRTL) -i $< -o $(generated_dir)/$(long_name).v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
cd $(generated_dir) && \