riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao
d5153bf42e don't connect unnecessary wires in regression test 2016-04-12 15:38:55 -07:00
Howard Mao
55df7d97cc add regression test for put immediately before put block 2016-04-12 15:38:55 -07:00
Howard Mao
485d8d7f9c fix nasti converter tests 2016-04-12 15:38:55 -07:00
Howard Mao
b2e15cd9bc NASTI to SMI converter test should also test TL to NASTI conversion 2016-04-12 15:38:55 -07:00
Howard Mao
0c562277db test Nasti to SMI converter with SMI datawidth being different 2016-04-12 15:38:55 -07:00
mwachs5
a81334f505 Update README links to point to this repo 2016-04-06 14:10:04 -07:00
Matthew Naylor
b2eabf4a9f Add tracegen scripts inc. bugfix from @mwachs5 
A step towards moving the tracegen scripts from rocket-chip to
groundtest.  I will raise an issue requesting that the scripts are now
removed from rocket-chip by someone with write access.

I have updated the README to account for the move.

This commit includes a bugfix from @mwachs5 (with slight mods by me)
relating to potential division by zero in toaxe.py.
 2016-04-06 15:15:48 +01:00
Andrew Waterman
7285f5e6bf Don't drive D$ kill/phys signals for SimpleHellaCacheIF 
They don't do anything.
 2016-04-01 19:31:54 -07:00
Matthew Naylor
6d3bba6cff Tweaks to README.md 
Remove occurrences of ../scripts/ and instead state that it must be in
your PATH.  Also drop the content introducing the isit script as
tracegen+check.sh subsumes this.
 2016-03-31 14:22:09 -07:00
mwachs5
22e7b3ff2f Update README.md 
- adding instructions of how to run with groundtest
- correct some MD syntax in README
- add some spaces
- minor changes to wording
- remove spurious 'class'
- add commands for running w/ TraceGenConfig
- add code from http://www.cl.cam.ac.uk/~mn416/tracegen.html
- Update README.md
- add WSO note
- correct some syntax within the code blocks and add note about run-asm-tests, run-bmark-tests
- Add one more command to the "quick reference" to show the complete flow
- Correct WSO to WMO
- Add information about tracegen+check.sh
- Use tracegen.py commands instead of running the emulator directly
- added a missing newline
- remove extra head command
 2016-03-31 14:20:14 -07:00
Howard Mao
af3bc1cb79 don't use ROM for partial writemask regression 2016-03-25 14:06:06 -07:00
Howard Mao
5372f181b1 add in missing connections for regression test 2016-03-25 14:05:52 -07:00
Howard Mao
471f4c2695 change WriteMaskedPutBlockRegression for better bug detection 
Instead of sending puts back-to-back, separate the two puts with a get.
Also, stall a bit between each transaction. This makes sure the puts and
intermediate get are sent to the same transactor, which will cause the
data buffer to get overwritten between the two puts.
 2016-03-23 16:31:19 -07:00
Howard Mao
3b0e87f42a pass CSRs through to ground test and get DMA tests working again 2016-03-22 20:18:02 -07:00
Howard Mao
7b7e954133 make sure DummyPTW does not invalidate the TLB 2016-03-22 19:59:58 -07:00
Matthew Naylor
bda5772e98 Updates to the trace-generator: (1) Don't terminate via HTIF exit, which can cause other, unfinished, cores to be cut short. Instead emit FINISHED messsages allowing an external process to send a SIGTERM to the emulator once all cores have finished. (2) Add some support for greater address variation without having to recompile, disabled by default. (3) Generate atomic, LR/SC, and fence operations by default in addition to plain loads and stores. These changes require newer versions of files in the rocket-chip/scripts directory. I will submit a pull request for those too. 2016-03-18 12:11:11 +00:00
Matthew Naylor
04be438847 Avoid conflicting assigments to registers in timers. Give priority to start over stop. 2016-03-16 12:54:19 -07:00
Andrew Waterman
137b77d780 Merge pull request #4 from ucb-bar/chisel3 
Work around Chisel3's lack of 0-width wires
 2016-03-15 17:30:34 -07:00
Palmer Dabbelt
50f61687de Work around Chisel3's lack of 0-width wires 
This is super ugly, but it's necessary to get Chisel3 to compile.  Note
that this still fails simulations in Chisel3, so it might be wrong.
 2016-03-14 22:50:37 -07:00
Andrew Waterman
13dcb96b7f Update TLB interface 
n.b. no need to set mprv, since prv = S.
 2016-03-14 17:55:19 -07:00
Andrew Waterman
3e721fe80b Merge pull request #2 from ucb-bar/chisel3 
Pass a BitPat to Lookup
 2016-03-06 04:27:52 -08:00
Palmer Dabbelt
bf06ba0d37 Pass a BitPat to Lookup 
This is the only supported type of Lookup in Chisel 3.
 2016-03-05 18:50:56 -08:00
Howard Mao
c2e9971b5f move toaxe.py script into top-level Rocket-Chip repo 2016-02-23 08:52:32 -08:00
Matthew Naylor
1b6871f3d8 Add author, affiliation, and sponsor info to trace-generator files. 2016-02-23 15:30:11 +00:00
Howard Mao
91e3c9b96f reuse generator parameters for tracegen 2016-02-22 09:53:31 -08:00
Matthew Naylor
e63fc3bb44 Added trace generator 2016-02-22 08:43:34 -08:00
Howard Mao
da302504a5 get rid of sequential same id get regression in broadcast regression suite 2016-02-19 23:14:34 -08:00
Howard Mao
000af5e662 add NastiIOHostIO converter test 2016-02-19 11:21:53 -08:00
Howard Mao
f290157cb3 check that MultiWidthFifo count is correct 2016-02-17 13:36:07 -08:00
Howard Mao
4915a258f6 add unit test for some modules 2016-02-16 23:10:55 -08:00
Howard Mao
e90dfcb403 add test for NASTI to TL converter 2016-02-10 11:07:37 -08:00
Howard Mao
428fa14601 fix DummyPTW response 2016-01-27 15:33:02 -08:00
Howard Mao
a59ff38b67 use MMIO for DMA requests instead of separate channel 2016-01-27 15:33:02 -08:00
Howard Mao
04e1f8c5c3 lowercase SMI to Smi 2016-01-11 16:18:49 -08:00
Howard Mao
80d97d5f9e test DMA streaming 2016-01-06 21:38:12 -08:00
Howard Mao
b8d0376d3f Merge pull request #1 from ucb-bar/dma 
add DMA test
 2015-12-22 10:33:48 -05:00
Howard Mao
24eecee148 add DMA test 2015-12-16 21:26:22 -08:00
Howard Mao
4858ca9a60 add a regression to test proper writeback 2015-12-16 21:05:56 -08:00
Howard Mao
176d3c890c add some more regression tests 2015-12-15 23:00:17 -08:00
Howard Mao
484e8ce20b add regression tests for catching specific memory bugs 2015-12-06 02:57:45 -08:00
Howard Mao
158d1d870c do all the writes before doing the gets in GeneratorTest 2015-11-21 09:42:00 -08:00
Howard Mao
49c6b1ad1c add CacheFillTest 2015-11-19 00:15:36 -08:00
Howard Mao
640544ea5a generalize test harness 2015-11-18 22:54:05 -08:00
Howard Mao
f325874420 make sure timeout doesn't trigger spuriously on reset 2015-11-18 22:53:50 -08:00
Howard Mao
8bc90ab9bd separate out common functionality 2015-11-18 20:53:19 -08:00
Howard Mao
10f4c6c71c interleave cached and uncached requests 2015-11-12 11:34:44 -08:00
Howard Mao
7cae6cedf5 finished bit should be set true if generator not being used 2015-11-11 18:51:16 -08:00
Howard Mao
f93872d6b4 make sure cached generator actually drives finished signal 2015-11-11 18:45:36 -08:00
Howard Mao
eeda3dd770 add README 2015-11-11 18:30:19 -08:00
Howard Mao
9482d944ca make Uncached generator vary the alloc bit 2015-11-11 18:26:56 -08:00