riscv/rocket-chip
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Author SHA1 Message Date
Palmer Dabbelt
0c695d8e83 Use the new TileLink to Smi converter (#10) 
I pulled out the TileLink to Smi converter and put it in uncore so I can
use it for my own stuff.
 2016-06-10 14:04:48 -07:00
Wesley W. Terpstra
5562241a50 comparator: a new TileLink stress-tester 2016-06-09 14:02:35 -07:00
Colin Schmidt
40b6e44816 name resetSignal parameter to tile constructor 
if the tile constructor were to change groundtest
only needs to be updated if resetSignal is removed or renamed
 2016-06-09 10:20:48 -07:00
Howard Mao
21feeb4a4f have multiple outstanding requests in CacheFillTest 2016-06-08 19:53:42 -07:00
Howard Mao
f44778fa56 make sure Cached generator comparison truncates to correct size 2016-06-06 17:45:04 -07:00
Howard Mao
022503748e make Memtest generators more configurable 2016-06-06 09:44:09 -07:00
Howard Mao
2163ebfca3 use a generic Nasti memory driver for unit tests 2016-06-06 09:43:39 -07:00
Andrew Waterman
cf8be98b2b Cope with changes to AddrMap 2016-06-03 13:48:43 -07:00
Howard Mao
a917f554fd use Wesley's test SRAM for AXI -> AHB converter test 2016-06-01 11:40:59 -07:00
Howard Mao
8f269b2eec stall for more cycles in Hasti test 2016-05-31 19:46:42 -07:00
Matthew Naylor
2a7e7172a9 Update docs for the trace generator 2016-05-27 10:54:35 +01:00
Andrew Waterman
75f06d6e84 Use generic TileLink width adapter 2016-05-26 16:00:17 -07:00
Matthew Naylor
b734beec06 Update build instructions 
The emulator now requires an ELF file even when running ground tests.
(The ELF contains the tohost and fromhost addresses for communication
with the FESVR.)
 2016-05-26 14:42:26 +01:00
Andrew Waterman
ddfa30e215 Work around zero-width wire limitations 2016-05-26 00:48:54 -07:00
Matthew Naylor
213bb26367 Drive invalidate_lr signal 
The DCache input for invalidating LR reservations was dangling.  Now
we wire it to false.
 2016-05-25 13:27:12 +01:00
Matthew Naylor
05c0808ff2 Update trace generation and checking scripts 
Pass the elf file (that specifies the tohost and fromhost addresses)
to the emulator in the trace generator & checker scripts.
 2016-05-23 17:02:15 +01:00
Howard Mao
87be2bcd60 make sure TraceGen addresses are correct 2016-05-20 16:12:11 -07:00
Howard Mao
3e759d2575 add Hasti test to unit test 2016-05-06 11:31:43 -07:00
Howard Mao
1882e694e4 only write to a single tohost location 2016-05-03 20:20:52 -07:00
Howard Mao
6cb0979ac4 fix CacheFillTest 2016-05-03 13:35:38 -07:00
Howard Mao
518d510622 only write out finish from tile 0 in groundtest 2016-05-03 13:09:22 -07:00
Howard Mao
b95f095aca write to multiple possible tohost locations 2016-05-02 20:11:20 -07:00
Howard Mao
4b4e8f7f62 fixes for priv-1.9 changes 2016-05-02 18:25:02 -07:00
Howard Mao
5e793427eb use address map instead of MMIOBase 2016-04-21 15:38:43 -07:00
Howard Mao
82cacfbc5e add NastiMemoryDemux to unit tests 2016-04-19 09:34:42 -07:00
Howard Mao
075fdfb847 use Atos serdes/desser in Atos unit test 2016-04-19 09:34:12 -07:00
Howard Mao
ee66da603a move AtosConverterTest into UnitTestSuite 2016-04-19 09:34:12 -07:00
Howard Mao
d19aaf8d89 test AtoS conversions and SERDES 2016-04-19 09:33:05 -07:00
Howard Mao
d5153bf42e don't connect unnecessary wires in regression test 2016-04-12 15:38:55 -07:00
Howard Mao
55df7d97cc add regression test for put immediately before put block 2016-04-12 15:38:55 -07:00
Howard Mao
485d8d7f9c fix nasti converter tests 2016-04-12 15:38:55 -07:00
Howard Mao
b2e15cd9bc NASTI to SMI converter test should also test TL to NASTI conversion 2016-04-12 15:38:55 -07:00
Howard Mao
0c562277db test Nasti to SMI converter with SMI datawidth being different 2016-04-12 15:38:55 -07:00
mwachs5
a81334f505 Update README links to point to this repo 2016-04-06 14:10:04 -07:00
Matthew Naylor
b2eabf4a9f Add tracegen scripts inc. bugfix from @mwachs5 
A step towards moving the tracegen scripts from rocket-chip to
groundtest.  I will raise an issue requesting that the scripts are now
removed from rocket-chip by someone with write access.

I have updated the README to account for the move.

This commit includes a bugfix from @mwachs5 (with slight mods by me)
relating to potential division by zero in toaxe.py.
 2016-04-06 15:15:48 +01:00
Andrew Waterman
7285f5e6bf Don't drive D$ kill/phys signals for SimpleHellaCacheIF 
They don't do anything.
 2016-04-01 19:31:54 -07:00
Matthew Naylor
6d3bba6cff Tweaks to README.md 
Remove occurrences of ../scripts/ and instead state that it must be in
your PATH.  Also drop the content introducing the isit script as
tracegen+check.sh subsumes this.
 2016-03-31 14:22:09 -07:00
mwachs5
22e7b3ff2f Update README.md 
- adding instructions of how to run with groundtest
- correct some MD syntax in README
- add some spaces
- minor changes to wording
- remove spurious 'class'
- add commands for running w/ TraceGenConfig
- add code from http://www.cl.cam.ac.uk/~mn416/tracegen.html
- Update README.md
- add WSO note
- correct some syntax within the code blocks and add note about run-asm-tests, run-bmark-tests
- Add one more command to the "quick reference" to show the complete flow
- Correct WSO to WMO
- Add information about tracegen+check.sh
- Use tracegen.py commands instead of running the emulator directly
- added a missing newline
- remove extra head command
 2016-03-31 14:20:14 -07:00
Howard Mao
af3bc1cb79 don't use ROM for partial writemask regression 2016-03-25 14:06:06 -07:00
Howard Mao
5372f181b1 add in missing connections for regression test 2016-03-25 14:05:52 -07:00
Howard Mao
471f4c2695 change WriteMaskedPutBlockRegression for better bug detection 
Instead of sending puts back-to-back, separate the two puts with a get.
Also, stall a bit between each transaction. This makes sure the puts and
intermediate get are sent to the same transactor, which will cause the
data buffer to get overwritten between the two puts.
 2016-03-23 16:31:19 -07:00
Howard Mao
3b0e87f42a pass CSRs through to ground test and get DMA tests working again 2016-03-22 20:18:02 -07:00
Howard Mao
7b7e954133 make sure DummyPTW does not invalidate the TLB 2016-03-22 19:59:58 -07:00
Matthew Naylor
bda5772e98 Updates to the trace-generator: (1) Don't terminate via HTIF exit, which can cause other, unfinished, cores to be cut short. Instead emit FINISHED messsages allowing an external process to send a SIGTERM to the emulator once all cores have finished. (2) Add some support for greater address variation without having to recompile, disabled by default. (3) Generate atomic, LR/SC, and fence operations by default in addition to plain loads and stores. These changes require newer versions of files in the rocket-chip/scripts directory. I will submit a pull request for those too. 2016-03-18 12:11:11 +00:00
Matthew Naylor
04be438847 Avoid conflicting assigments to registers in timers. Give priority to start over stop. 2016-03-16 12:54:19 -07:00
Andrew Waterman
137b77d780 Merge pull request #4 from ucb-bar/chisel3 
Work around Chisel3's lack of 0-width wires
 2016-03-15 17:30:34 -07:00
Palmer Dabbelt
50f61687de Work around Chisel3's lack of 0-width wires 
This is super ugly, but it's necessary to get Chisel3 to compile.  Note
that this still fails simulations in Chisel3, so it might be wrong.
 2016-03-14 22:50:37 -07:00
Andrew Waterman
13dcb96b7f Update TLB interface 
n.b. no need to set mprv, since prv = S.
 2016-03-14 17:55:19 -07:00
Andrew Waterman
3e721fe80b Merge pull request #2 from ucb-bar/chisel3 
Pass a BitPat to Lookup
 2016-03-06 04:27:52 -08:00
Palmer Dabbelt
bf06ba0d37 Pass a BitPat to Lookup 
This is the only supported type of Lookup in Chisel 3.
 2016-03-05 18:50:56 -08:00