Henry Cook
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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Henry Cook
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4eaab214d2
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:29:51 -07:00 |
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Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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Henry Cook
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569d8fd796
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Merge branch 'tilelink-data'
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2013-05-23 14:14:40 -07:00 |
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Yunsup Lee
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11133d6d4c
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clock gate s2 registers in the frontend
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2013-05-21 18:59:21 -07:00 |
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Henry Cook
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69b508ff39
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ported caches and htif to use new tilelink
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2013-05-21 17:21:04 -07:00 |
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Yunsup Lee
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dcde377303
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Fix DM I$ deadlock
BTB predictions were causing infinite miss loops
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2013-05-20 15:22:58 -07:00 |
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Andrew Waterman
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6eb4c2542a
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comment out I$ assert for now
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2013-05-18 18:09:23 -07:00 |
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Andrew Waterman
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dfa7a03f73
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use assert, not Assert
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2013-05-18 00:45:13 -07:00 |
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Andrew Waterman
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d405ffa949
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assume all I$ grants bear data
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2013-05-01 21:01:20 -07:00 |
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Henry Cook
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95f0a688e9
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Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
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2013-03-20 17:37:50 -07:00 |
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Henry Cook
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273bd34091
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Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
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2013-03-20 15:53:36 -07:00 |
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Andrew Waterman
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ea9d0b771e
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remove aborts; simplify probes
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2013-03-19 15:29:40 -07:00 |
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Henry Cook
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e0361840bd
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writebacks on release network pass asm tests and bmarks
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2013-02-28 18:11:40 -08:00 |
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Andrew Waterman
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35349d227f
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update to new Mem style
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2013-02-20 16:09:46 -08:00 |
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Henry Cook
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f5729c9f25
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removed ack_required field from grant messages
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2013-01-28 16:44:17 -08:00 |
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Rimas Avizienis
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63060bc0a8
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minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
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2013-01-23 19:27:53 -08:00 |
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Henry Cook
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6b00e7ff74
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New TileLink bundle names
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2013-01-21 17:18:23 -08:00 |
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Henry Cook
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a2fa3fd04d
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Refactored packet headers/payloads
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2013-01-15 15:50:37 -08:00 |
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Henry Cook
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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de2f28193a
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get rid of more global constants
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2012-11-25 04:24:25 -08:00 |
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Andrew Waterman
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b514c7b725
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clean up I$ parity code
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2012-11-24 22:00:43 -08:00 |
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Andrew Waterman
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ff8c736d94
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move icache invalidate out of request bundle
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2012-11-16 01:55:45 -08:00 |
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Andrew Waterman
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4d1ca8ba3a
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remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
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2012-11-06 08:13:44 -08:00 |
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Andrew Waterman
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c5b93798fb
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factor out more global constants
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2012-11-05 23:52:32 -08:00 |
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Andrew Waterman
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e9eca6a95d
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refactor I$ config; remove Top class
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2012-11-04 16:59:36 -08:00 |
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Andrew Waterman
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bd2d61de03
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use 8T SRAM for I$; gate clock more aggressively
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2012-11-04 16:39:25 -08:00 |
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Henry Cook
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88ac5af181
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Merged consts-as-traits
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2012-10-16 16:32:35 -07:00 |
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Andrew Waterman
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5821900329
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don't refetch from I$ if on same 16B block
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2012-10-16 02:24:38 -07:00 |
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Andrew Waterman
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661f8e635b
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merge I$, ITLB, BTB into Frontend
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2012-10-16 02:24:37 -07:00 |
|
Henry Cook
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8970b635b2
|
improvements to implicit RocketConfiguration parameter
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2012-10-15 16:29:49 -07:00 |
|
Henry Cook
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9025d0610c
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first pass at configuration object passed as implicit parameter
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2012-10-07 22:37:29 -07:00 |
|
Henry Cook
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dfdfddebe8
|
constants as traits
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2012-10-07 22:20:03 -07:00 |
|
Huy Vo
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e909093f37
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factoring out uncore into separate uncore repo
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2012-10-01 16:08:41 -07:00 |
|
Henry Cook
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b9a9664de5
|
uncore and rocket changes for new xact types
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2012-10-01 10:47:36 -07:00 |
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Andrew Waterman
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0f20771664
|
rename queue to Queue
fixes build with case-insensitive file system
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2012-08-08 22:11:59 -07:00 |
|
Huy Vo
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fd95159837
|
INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
|
Andrew Waterman
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bac82762d3
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use only one (wide) tag ram for set assoc. caches
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2012-07-12 14:50:12 -07:00 |
|
Andrew Waterman
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4e5f874266
|
update to new chisel/hwacha
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2012-06-08 00:13:14 -07:00 |
|
Huy Vo
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04304fe788
|
moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
|
Huy Vo
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c975c21e44
|
views removed
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2012-06-06 12:51:26 -07:00 |
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Andrew Waterman
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7f6319047e
|
update to new scala/chisel/Mem
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2012-06-06 02:47:22 -07:00 |
|
Huy Vo
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7408c9ab69
|
removing wires
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2012-05-24 10:42:39 -07:00 |
|
Andrew Waterman
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eafdffe125
|
simplify page table walker; speed up emulator
|
2012-05-01 01:24:36 -07:00 |
|
Henry Cook
|
3cdd166153
|
Refactored coherence as member rather than trait. MI and MEI protocols.
|
2012-04-10 00:09:58 -07:00 |
|
Henry Cook
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0b4937f70f
|
changed coherence message type names
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2012-04-09 23:29:31 -07:00 |
|
Yunsup Lee
|
32d95e9594
|
fix -1:0 index problem for direct map case
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2012-03-26 17:00:01 -07:00 |
|
Henry Cook
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22726ae646
|
icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data
|
2012-03-08 18:47:32 -08:00 |
|
Andrew Waterman
|
6e16b04ada
|
implement transaction finish messages
|
2012-03-06 15:48:08 -08:00 |
|
Andrew Waterman
|
5f12990dfb
|
support memory transaction aborts
|
2012-03-06 00:35:02 -08:00 |
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