riscv/rocket-chip
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647 Commits

Author SHA1 Message Date
Andrew Waterman
9518b3d589 Fix arithmetic in ROM row count 2016-06-01 21:59:02 -07:00
Andrew Waterman
8e80d1ec80 Avoid floating-point arithmetic where integers suffice 2016-06-01 21:59:02 -07:00
Wesley W. Terpstra
11b3cee07a Ahb tweaks (#50) 
* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully

I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.

* ahb: optionally disable atomics => optimize to nothing

Trust the compiler the compiler to optimize away unused logic.
 2016-06-01 16:42:39 -07:00
mwachs5
740a6073f6 Add Debug Module (#49) 
* Add Debug Module

* [debug] Remove unit tests, update System Bus register addresses, parameterize nComponents

* [debug] Update Debug ROM contents to match updated addresses
 2016-06-01 16:33:33 -07:00
Howard Mao
e8408f0a8a fix HastiRAM 2016-06-01 10:33:59 -07:00
Andrew Waterman
6d82c0d156 Add M_FLUSH_ALL command 2016-05-31 19:25:31 -07:00
Andrew Waterman
8afdd7e3da Work around PutBlocks draining into data array prematurely 2016-05-26 23:08:05 -07:00
Andrew Waterman
391a9b9110 Use buses, rather than crossbars, by default in TLInterconnect 
We should eventually parameterize this, of course.
 2016-05-26 16:10:42 -07:00
Andrew Waterman
b6d26e90f8 Add generic TileLink width adapter 2016-05-26 15:59:42 -07:00
Andrew Waterman
8139f71dfb Work around Chisel2 bug 
This code is correct, but Chisel2 erroneously flags it as a Chisel3
compatibility error because it looks like Vec(Reg) when factor=1.
 2016-05-26 12:37:31 -07:00
Andrew Waterman
22568de5f3 Work around another zero-width wire limitation 2016-05-25 21:42:02 -07:00
Andrew Waterman
e2755a0f0a Work around zero-width wire limitation in HTIF 2016-05-25 20:39:53 -07:00
Andrew Waterman
3e238adc67 rtc: fix acquire message type check 2016-05-25 20:37:48 -07:00
Wesley W. Terpstra
7f1792cba3 ahb: backport bridge to chisel2 
Closes #47
 2016-05-25 13:40:24 -07:00
Andrew Waterman
c49cb10c74 Merge pull request #42 from terpstra/ahb 
Ahb
 2016-05-24 17:02:15 -07:00
Andrew Waterman
88cc91db75 Ignore way_en in MetadataArray for direct-mapped caches 2016-05-24 15:47:09 -07:00
Wesley W. Terpstra
a012341d96 ahb: TileLink => AHB bridge, including atomics and bursts 2016-05-24 14:58:27 -07:00
Wesley W. Terpstra
ace9362d81 ahb: amoalu does not need so many parameters! (i want to reuse it) 2016-05-24 14:58:27 -07:00
Wesley W. Terpstra
00d31dc5c5 bram: use new hasti definitions 2016-05-24 13:35:16 -07:00
Albert Ou
ee0acc1d07 Fix BRAM assertion condition 2016-05-23 13:19:53 -07:00
Colin Schmidt
3e0b5d6fd9 Ensure that a TSHR doesn't see a valid Acquire if that is blocked by a Release, 
but would otherwise be allocated.

Closes #45
 2016-05-20 16:35:30 -07:00
Ken McMillan
fd83d20857 Use a def instead of a lazy val in ManagerCoherenceAgent. 
Prevents C++ emulator from randomizing inputs in unit testing.

Closes #44
 2016-05-20 16:31:12 -07:00
Ken McMillan
d69446e177 Add config classes to drive unit testing of L2 TileLink agents. 
Closes #43
 2016-05-20 16:15:43 -07:00
Howard Mao
4f84d8f757 make sure to hook up finish in ClientTileLinkEnqueuer 2016-05-18 13:13:34 -07:00
Howard Mao
f138819992 fix order of assignments in ManagerTileLinkNetworkPort 2016-05-11 16:45:00 -07:00
Andrew Waterman
533b229175 Improve PLIC QoR 2016-05-10 17:03:56 -07:00
Andrew Waterman
e15e9c5085 First draft of interrupt controller 2016-05-10 00:25:13 -07:00
Howard Mao
14a6e470c9 transform ids in TL -> NASTI converter if necessary 2016-05-07 21:19:27 -07:00
Howard Mao
1ed6d6646d move NastiROM and HastiRAM into rom.scala and bram.scala 2016-05-06 11:31:22 -07:00
Howard Mao
77e859760c add a Hasti RAM alongside the Nasti ROM 2016-05-06 11:31:22 -07:00
Howard Mao
f26c422544 assert that TileLink router has valid route 2016-05-03 12:18:06 -07:00
Andrew Waterman
cc4102f8de Add trivial version of PRCI block 
It doesn't really do anything besides deliver deliver IPIs yet.
 2016-05-02 17:49:10 -07:00
Andrew Waterman
72731de25a Take a stab at the PRCI-Rocket interface 2016-05-02 15:20:33 -07:00
Andrew Waterman
695c4c5096 Support both Get and GetBlock on ROMSlave 2016-04-30 17:34:12 -07:00
Albert Ou
6f052a740c Add TileLink BRAM slave 2016-04-29 14:10:44 -07:00
Andrew Waterman
1df68a25fd Address Map refactoring 2016-04-28 16:08:58 -07:00
Wei Song
ed5bdf3c23 print the base address of each SCR as indicated 2016-04-28 16:31:56 +01:00
Andrew Waterman
81ff127dc3 Clean up TileLinkRecursiveInterconnect a bit 2016-04-27 14:53:11 -07:00
Andrew Waterman
87cecc336f Add new RTC as TileLink slave, not AXI master 2016-04-27 11:55:35 -07:00
Andrew Waterman
eb0b5ec61e Remove stats CSR 2016-04-27 00:16:21 -07:00
Andrew Waterman
9044a4a4b7 Replace NastiROM with ROMSlave, which uses TileLink 
I'm not wedded to the name.
 2016-04-27 00:15:30 -07:00
Andrew Waterman
356efe2fd5 Simplify TileLink Narrower 
It's not necessary to use addr_beat to determine where to put the Grant
data.  Just stripe it across all lanes.

This also gets rid of a dependence on addr_beat in Grant.  If we move
towards a regime where TileLink is only narrowed, not widened, we may
be able to drop the field altogether.
 2016-04-26 16:44:54 -07:00
Wei Song
f6e44b1348 avoid logical to physical header conversion overflow 2016-04-22 17:47:34 +01:00
Howard Mao
f9de99ed40 changes to match junctions no-mmio-base 2016-04-21 15:35:37 -07:00
Howard Mao
9b3faff5a5 add id field to write data channel in TL -> AXI converter 2016-04-19 09:46:31 -07:00
Howard Mao
152645b1bc use manager_id instead of client_id in GrantFromSrc and FinishToDst 2016-04-07 11:20:16 -07:00
Howard Mao
f88b6932ce don't add pending reads if data is already available 2016-04-06 15:43:21 -07:00
Howard Mao
31e145eaf0 fix BroadcastHub allocation and routing 2016-04-05 16:21:18 -07:00
Howard Mao
f68a7dabdf fix AXI -> TL converter 2016-04-04 19:42:25 -07:00
Howard Mao
f956d4edfb NASTI does not right-justify data; fix in converter 2016-04-01 20:55:00 -07:00
Henry Cook
c292a07ace Bugfix for merged voluntary releases in L2Cache. 
Track pending release beats for voluntary releases that are merged by Acquire Trackers.
Closes #23 and #24.
 2016-04-01 19:57:47 -07:00
Henry Cook
82bdf3afcb Fix LRSC starvation bug by punching Finish messages out to caching clients via a new TileLinkNetworkPort. 2016-04-01 16:17:27 -07:00
Andrew Waterman
8957b5e973 Improve simulation speed of BasicCrossbar 2016-04-01 13:28:11 -07:00
Howard Mao
3083bbca21 fix TileLink arbiters and add memory interconnect and memory selector 2016-03-31 18:15:51 -07:00
Howard Mao
cf363b1fe4 add TileLink interconnect generator 2016-03-31 14:12:55 -07:00
Howard Mao
d78066db5c chisel3 fix for split metadata 2016-03-30 22:11:19 -07:00
Howard Mao
3d990bdbef workaround for Chisel3 name-aliasing issue 2016-03-30 19:15:22 -07:00
Howard Mao
8e7f18084b switch RTC to use TileLink instead of AXI 2016-03-28 12:23:16 -07:00
Howard Mao
7f8f138d6a fix addPendingBitWhenPartialWritemask 2016-03-24 20:01:50 -07:00
Howard Mao
11bd15432a fix bug in RTC 2016-03-24 20:01:50 -07:00
Howard Mao
00b3908d92 git rid of reorder queue in narrower 2016-03-24 20:01:50 -07:00
Palmer Dabbelt
c9e1b72972 Don't assign SInt(-1) to a UInt 2016-03-23 16:24:27 -07:00
Palmer Dabbelt
aa22f175c3 Add cloneType methods for Chisel3 2016-03-21 13:35:02 -07:00
Palmer Dabbelt
1344d09cef Fix the SCR file for Chisel 3 2016-03-21 11:55:18 -07:00
Henry Cook
c13b8d243d BroadcastHub race on allocating VolWBs vs Acquires 2016-03-17 18:32:35 -07:00
Henry Cook
5f3d3a0b2d Bugfix for probe flags in L2BroadcastHub 
Closes #25
 2016-03-17 16:42:40 -07:00
Henry Cook
49d82864bf Fix StoreDataQueue allocation bug in BroadcastHub 
Closes #27
 2016-03-17 12:31:18 -07:00
Eric Love
8a47c3f346 Make sure there's enough xact id bits 2016-03-16 13:49:30 -07:00
Henry Cook
67e711844a index extraction bug 2016-03-10 17:37:40 -08:00
Palmer Dabbelt
e2185d40f6 Avoid right-shift by larger that the bit width 
FIRRTL bails out on this.  There's an outstanding bug, this is just a
workaround.  See https://github.com/ucb-bar/firrtl/issues/69
 2016-03-10 17:37:40 -08:00
Palmer Dabbelt
8c7e29eacd Avoid generating 0-width UInts 
Chisel3 requires a 1-bit width to represent UInt(0).
 2016-03-10 17:37:40 -08:00
Andrew Waterman
2eafc4c8f3 Extend AMOALU to support RV32 2016-03-10 17:32:23 -08:00
Andrew Waterman
c28d115b30 Chisel3 compatibility fix 2016-03-10 17:32:23 -08:00
Henry Cook
93773a4496 Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks. 
To elide several races between reading and writing the metadata array for different types of transactions, all L2XactTrackers can now sink Voluntary Releases (writebacks from the L1 in the current implementation). These writebacks are merged with the ongoing transaction, and the merging tracker supplies an acknowledgment of the writeback in addition to its ongoing activities. This change involved another refactoring of the control logic for allocating new trackers and routing incoming Acquires and Releases. BroadcastHub uses the new routing logic, but still processes all voluntary releases through the VoluntaryReleaseTracker (not a problem because there are no metadata update races).

Closes #18
Closes #20
 2016-03-10 17:14:34 -08:00
Andrew Waterman
36f2e6504c Fix width of NastiROM rows, preventing out-of-range extraction 2016-03-03 16:57:16 -08:00
Henry Cook
7eef3393f1 fix bug resulting in different g_types on tail beats in L2CacheBank.io.inner.grant 2016-03-02 14:11:45 -08:00
Henry Cook
57370bdf49 first and last on HasTileLinkData 2016-03-02 14:11:39 -08:00
Palmer Dabbelt
4acdc67485 Add an assertion in the NastiIOTileLink converter 
This uses an reorder queue but doesn't check to ensure that the data it fetches
from the queue is actually in the queue before using it.  It seems that during
correct operation this never breaks, but I'm trying to get the backup memory
port working again and this assertion fails with it enabled (without the
assertion the core just gets a bogus data beat dies).

Closes #16
 2016-03-01 12:23:32 -08:00
Albert Magyar
ab30983aa9 Add support for per-way cache metadata 
Exposes new parameter field SplitMetadata to determine whether the metadata array in a particular cache is stored in a single SeqMem or with one SeqMem per way.

Closes #14
 2016-03-01 12:19:42 -08:00
Howard Mao
6d984273b7 finally fix all release assertions ... hopefully 2016-02-29 15:22:24 -08:00
John Wright
6095e7361e Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip 2016-02-27 16:19:25 -08:00
Palmer Dabbelt
ebffd69b8e Provide both __OFFSET and __PADDR for SCR entries 
This was recently changed to write out physical addresses for SCR file entries,
but to bring up the chip we need SCR offsets so we can write the uncore SCR
file over HTIF.  This changes the map generator to generate both.

Without this change things happened to work anyway because the high bits were
getting dropped by the SCR file.
 2016-02-25 21:48:32 -08:00
John Wright
19420cd5df add utility overloads of SCRIO.attach, pass base address so that generated c header is correct, and print debug messages/header in hex instead of decimal 2016-02-24 15:26:55 -08:00
Howard Mao
8873222e42 fix cache release assertion 2016-02-23 16:03:51 -08:00
Henry Cook
929d8e31f7 refactor ready/valid logic for routing release messages in the l2 2016-02-19 16:30:26 -08:00
Howard Mao
f97bd70df5 add NastiIO to HostIO converter 2016-02-19 11:21:23 -08:00
Palmer Dabbelt
1ac9f59b31 Allow SCR files to be enumerated in C headers 
Right now there's no way to ensure that SCR addresses don't conflict within
RocketChip.  Since upstream only has one of them this isn't a big deal, but we
want to add a whole bunch more to control all the IP on Hurricane.

This patch adds some Scala code to allocate registers inside the SCR file,
ensure they don't conflict, to provide names for SCRs, attach registers to the
SCR file, and generate a C header file that contains the addresses of every SCR
on a chip.

With this patch we'll be able to get rid of that constant in the testbench.
This also allows us to kill one of the Raven diffs, which is does pretty much
the same thing (just in a second SCR file, and hacked in).
 2016-02-17 14:21:12 -08:00
Howard Mao
53ad8387cc add NASTI to TL converter 2016-02-10 11:06:52 -08:00
Howard Mao
2825b2d645 make sure TL to NASTI converter handles MT_WU 2016-02-10 11:06:41 -08:00
Howard Mao
66e9cc8c82 make sure CSR width is parameterizable 2016-02-02 12:49:58 -08:00
Howard Mao
adaec18bec add TL manager for MMIO requests 2016-02-02 12:49:58 -08:00
Howard Mao
c1fe188c81 some fixes to RTC 2016-02-02 12:49:58 -08:00
Howard Mao
ba94010928 DMA requests should go through MMIO 2016-02-02 12:49:58 -08:00
Howard Mao
0dc8cd5b11 move ReorderQueue and DecoupledHelper to junctions 2016-01-21 15:36:22 -08:00
Andrew Waterman
2946bc928e Avoid muxing between bundles of different size 2016-01-16 19:01:24 -08:00
Howard Mao
4ff1aea288 fix more Chisel3 deprecations 2016-01-14 14:55:45 -08:00
Andrew Waterman
0b90b8fe5f Avoid zero-width wire case :-/ 2016-01-12 15:32:29 -08:00
Andrew Waterman
a953ff384a Chisel3 compatibility: use more concrete types 2016-01-12 15:32:14 -08:00
Howard Mao
c81745eb8e lowercase SMI to Smi 2016-01-11 16:18:44 -08:00
Howard Mao
d0a14c6de9 separate TileLink converter/wrapper/unwrapper/narrower into separate file 2016-01-11 16:14:56 -08:00