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Andrew Waterman 391a9b9110 Use buses, rather than crossbars, by default in TLInterconnect
We should eventually parameterize this, of course.
2016-05-26 16:10:42 -07:00
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2015-04-29 13:18:26 -07:00
2015-04-29 13:18:26 -07:00
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Uncore Library

This is the repository for uncore components assosciated with Rocket chip project. To uses these modules, include this repo as a git submodule within the your chip repository and add it as a project in your chip's build.scala. These components are only dependent on the ucb-bar/chisel repo, i.e.

lazy val uncore = project.dependsOn(chisel)

ScalaDoc for the uncore library is available here and an overview of the TileLink Protocol is available here, with associated CoherencePolicy documentation here.