History

Wesley W. Terpstra 11b3cee07a Ahb tweaks (#50 )

* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully

I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.

* ahb: optionally disable atomics => optimize to nothing

Trust the compiler the compiler to optimize away unused logic.

2016-06-01 16:42:39 -07:00

project

add plugins to make scala doc site and publish to ghpages

2015-04-29 15:34:56 -07:00

src/main/scala

Ahb tweaks (#50 )

2016-06-01 16:42:39 -07:00

.gitignore

First pages commit

2015-04-29 13:18:26 -07:00

build.sbt

Add ability to generate libraryDependency on cde.

2015-10-22 09:57:02 -07:00

LICENSE

First pages commit

2015-04-29 13:18:26 -07:00

README.md

update README.md

2015-07-29 11:49:21 -07:00

README.md

Uncore Library

This is the repository for uncore components assosciated with Rocket chip project. To uses these modules, include this repo as a git submodule within the your chip repository and add it as a project in your chip's build.scala. These components are only dependent on the ucb-bar/chisel repo, i.e.

lazy val uncore = project.dependsOn(chisel)

ScalaDoc for the uncore library is available here and an overview of the TileLink Protocol is available here, with associated CoherencePolicy documentation here.