riscv/rocket-chip
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82169e971e0e3201daec86ce9ec34bf64e9cd238
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Howard Mao 82169e971e Dynamically compute number of L1 client channels 
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.

This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
 2016-06-20 13:02:31 -07:00
Howard Mao 1679cf4764 fix groundtest tilelink xacts 2016-06-09 15:42:44 -07:00
Howard Mao 65b62a9e5f unbreak the emulator 2016-06-08 15:38:39 -07:00
Howard Mao 40ab0a7960 fix TL width adapter and make it easier to switch inner data width 2016-06-08 15:38:39 -07:00
Howard Mao a809a1712a make sure clocks and reset signals get intialized properly 2016-06-08 15:38:39 -07:00
Howard Mao 08e53a00f0 bump cde for better match failure stack trace 2016-06-07 16:15:10 -07:00
Howard Mao 2cd897e240 Revert "include the unmatched field in CDEMatchError" 
This reverts commit ff2937a788.
 2016-06-07 16:13:01 -07:00
Howard Mao 8db27a36c4 fix Tile reset power on behavior 2016-06-07 11:06:38 -07:00
Howard Mao 172c4f25f4 bump groundtest and uncore 2016-06-06 17:45:30 -07:00
Howard Mao ff2937a788 include the unmatched field in CDEMatchError 2016-06-06 11:23:20 -07:00
Howard Mao 50e3caef36 get rid of Zscale file I missed last time 2016-05-31 14:33:38 -07:00
Howard Mao f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Howard Mao df479d7935 don't make MIFTagBits a computed parameter 2016-05-08 11:04:58 -07:00
Howard Mao 3b0e9167fa add AXI to AHB converter and more conformant HASTI RAM 2016-05-06 11:32:03 -07:00
Howard Mao a875eb9c31 update riscv-tools for bbl fix 2016-05-05 19:36:34 -07:00
Howard Mao 18ffe7b1ec don't use +verbose in vsim .run rule 2016-05-04 23:01:14 -07:00
Howard Mao f1baa4aecc update riscv-tests so that mm benchmark doesn't run forever 2016-05-04 21:28:55 -07:00
Howard Mao dfcb73b6c9 groundtest only needs to write to a single tohost 2016-05-03 20:21:13 -07:00
Howard Mao 4045a07eda Remove need for separate riscv-tests for groundtest 2016-05-03 18:29:46 -07:00
Howard Mao 8f891437b5 fix CacheFillTest 2016-05-03 14:57:05 -07:00
Howard Mao 487d0b356e fixes to get groundtest working with priv-1.9 changes 2016-05-03 13:09:44 -07:00
Howard MaoandAndrew Waterman f7af908969 put memory into the address map and no longer use MMIOBase 2016-04-21 18:53:16 -07:00
Howard Mao 325d3671c4 add write data id field for AXI3 compat 2016-04-20 09:21:43 -07:00
Howard Mao 0cf6b1f118 merge ATOS changes from hurricane 2016-04-20 09:21:43 -07:00
Howard Mao c5838dd9b3 Fix narrow read/write behavior for AXI converters and fix L2 bugs 
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
 2016-04-12 15:39:15 -07:00
Howard Mao 5337c7d22d add more complicated memtests to travis 2016-03-31 18:42:14 -07:00
Howard Mao 4f06a5ff6b add memtest config for testing memory channel mux 2016-03-31 18:41:56 -07:00
Howard Mao 5a74a9b1e7 switch memory interconnect from AXI to TileLink 2016-03-31 18:18:30 -07:00
Howard Mao 6d5c98da7d point submodule pointer to proper commit hash 2016-03-31 15:03:33 -07:00
Howard MaoandHenry Cook 7c3b57b8fa switch MMIO network to TileLink 2016-03-31 14:30:10 -07:00
Howard Mao ab540d536a bump uncore for split metadata chisel3 fix 2016-03-30 22:11:45 -07:00
Howard Mao c831a0a4e5 use scala firrtl instead of stanza firrtl 2016-03-30 19:35:25 -07:00
Howard Mao be612e3843 bump rocket and uncore 2016-03-30 19:23:19 -07:00
Howard Mao c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter" 
This reverts commit 5378f79b50.
 2016-03-30 19:06:32 -07:00
Howard Mao e77900f540 Revert "switch back to Chisel2 for verilog build for now" 
This reverts commit 3673365b08.
 2016-03-30 19:00:38 -07:00
Howard Mao 8e601f26e1 switch back to the correct chisel3 and firrtl branches 2016-03-30 18:59:33 -07:00
Howard Mao 1e03408323 get rid of mt benchmark suite 2016-03-29 20:16:07 -07:00
Howard Mao cf716fea58 fix mm_dramsim2 2016-03-29 20:16:07 -07:00
Howard Mao 3673365b08 switch back to Chisel2 for verilog build for now 2016-03-29 20:16:07 -07:00
Howard Mao 265a82427e add DefaultL2Config and DualCoreConfig to travis 2016-03-29 20:16:07 -07:00
Howard Mao ad93e0226d Changes to prepare for switch to TileLink interconnect 
We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.

* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
 2016-03-29 20:16:07 -07:00
Howard Mao 38649bd4c1 some edits to groundtest regression tests 2016-03-29 20:16:07 -07:00
Howard Mao 9b9c662952 fix w_last wire 2016-03-29 20:16:07 -07:00
Howard Mao 2b61f28356 don't test DMA controller for now 2016-03-29 20:16:07 -07:00
Howard Mao e1a03cc9ac fix issue with partial writemasks 2016-03-29 20:16:07 -07:00
Howard Mao e90a9dfb2b make taking max of multiple integers in config a bit easier 2016-03-16 14:35:08 -07:00
Howard Mao 3c9e63f5a5 don't make HTIF clock divider tied to backup memory 2016-03-09 14:58:20 -08:00
Howard Mao 5e145515e1 fix some Chisel assertions 2016-03-02 14:50:49 -08:00
Howard Mao 760893e448 add makefile for float_fix and comlog tools 2016-02-29 11:24:53 -08:00
Howard Mao be8a411f9c get rid of axe submodule and move toaxe.py script to scripts 2016-02-29 10:59:19 -08:00
Howard Mao 8a877fa620 Add Matthew Naylor's trace generator and AXE scripts 2016-02-24 14:39:11 -08:00
Howard Mao 8c02cb09ca some additions to Travis and fixes for Testing 2016-02-23 23:37:29 -08:00
Howard Mao 4fedd180ee bump uncore and groundtest 2016-02-19 23:31:09 -08:00
Howard Mao 85cc632d5d fix emulator debug build 2016-02-19 23:13:57 -08:00
Howard Mao 5e4a02038c move FPGA AXI to HTIF converter into Chisel module 2016-02-19 13:53:31 -08:00
Howard Mao 9fb2216548 get rid of unused external mmio port 2016-02-10 21:49:02 -08:00
Howard Mao 4b95374f0c bump rocket for bug fixes 2016-02-10 11:12:48 -08:00
Howard Mao 72a876bfba add NASTI to TL converter 2016-02-10 11:12:39 -08:00
Howard Mao 06c3f9b655 Rocket Chip fixes in response to lowRISC team's comments 
* DMA frontend-backend communication tunneled over TileLink/AXI
 * Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
 * Don't make NIOMSHRs configurable. Fixed at 1.
 * Connect accelerator-internal CSRs into the CSR file
 * Make mtvec register configurable and writeable
 2016-02-02 13:14:52 -08:00
Howard Mao ff79a44eb0 move some utility code from uncore to junctions 2016-01-21 15:39:09 -08:00
Howard Mao 04fd407c3e bump rocket submodule pointer 2016-01-15 15:29:23 -08:00
Howard Mao 3b4b7126ed Chisel3 compile-time deprecations should be runtime errors 2016-01-14 15:12:41 -08:00
Howard Mao 33aa64212d fix more Chisel3 deprecations 2016-01-14 15:06:30 -08:00
Howard Mao c06884b78c lowercase SMI to Smi 2016-01-11 17:44:10 -08:00
Howard Mao 806e40d19b implement DMA streaming functionality 2016-01-07 19:26:15 -08:00
Howard Mao 2f71a3da5a bump up submodule commits to merge commits 
Github's PR system doesn't work so well with submodules, since it always
creates merge commits. We should probably avoid using it in the future.
 2015-12-22 08:09:24 -08:00
Howard Mao 0f51ca4c10 Merge pull request #35 from ucb-bar/dma 
Implement DMA unit
 2015-12-22 10:33:59 -05:00
Howard Mao 8190bf6e18 implement DMA unit 2015-12-16 21:27:48 -08:00
Howard Mao 1a272677ca more fixes to L2 cache 2015-12-16 21:06:39 -08:00
Howard Mao 560fdc19a8 add PLRU replacement option to L2 cache 2015-12-16 10:24:57 -08:00
Howard Mao 7ad9deeaee Fix issues with request merging in L2 cache and add regression tests 
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
 2015-12-15 23:02:15 -08:00
Howard Mao 0c91e00676 move GroundTest configs to a separate file 2015-12-06 03:01:05 -08:00
Howard Mao 4f5dabcda2 add SCR file to device tree 2015-12-05 00:28:58 -08:00
Howard Mao 6fc1e92708 add option to print cycle count regardless of exit status 2015-12-04 12:04:13 -08:00
Howard Mao f35b83d3ca allow configuration of rocket ICache buffering 2015-12-02 17:18:39 -08:00
Howard Mao ebf2417a32 rocc-fpu-port merged into master for rocket 2015-12-02 09:02:43 -08:00
Howard Mao cdc476a370 change Rocc parameterization 2015-12-01 17:56:09 -08:00
Howard Mao c8c68e75bb base NGenerators on NTiles, not the other way around 2015-12-01 15:26:09 -08:00
Howard Mao e4043570bd bump groundtest and hardfloat 2015-11-30 18:06:15 -08:00
Howard Mao 40d68406d6 use xlen parameter for ALU 2015-11-30 18:04:44 -08:00
Howard Mao 23f0756978 implement support for multiple RoCC accelerators 2015-11-26 12:49:04 -08:00
Howard Mao ec6bfde9a3 fix WritebackUnit issue in uncore 2015-11-21 16:11:22 -08:00
Howard Mao 9d50f37289 fix unused set issue for multiple L2 cache banks 2015-11-20 23:26:28 -08:00
Howard Mao ad3b7fd0e1 adjust CacheFillTest configuration 2015-11-19 10:52:14 -08:00
Howard Mao 4806f72b08 add CacheFillTest to check L2 conflict misses 2015-11-19 00:16:28 -08:00
Howard Mao 3514b6eb87 add some more useful configurations 2015-11-18 22:11:17 -08:00
Howard Mao 379d43d5f4 make MultiChannel routing more performant 2015-11-18 22:11:17 -08:00
Howard Mao a1063bad54 fix issues with non-allocating put/get 2015-11-12 15:54:34 -08:00
Howard Mao 6ddf81090b didn't mean to turn off GenerateCached in last commit 2015-11-11 17:39:08 -08:00
Howard Mao 11f0b3d8db restore old L2 cache AcquireTransactor configuration 2015-11-11 17:10:58 -08:00
Howard Mao 31da692ccc default to single tile in WithMemtest 2015-11-11 14:54:13 -08:00
Howard Mao 55581195eb add groundtest submodule for simple memory testing 2015-11-11 14:33:02 -08:00
Howard Mao 149480411e make sure ClientTileLinkEnqueuer uses the correct parameters 2015-11-10 16:09:19 -08:00
Howard Mao 51f128ec74 actually use backendBuffering in front of unwrapper/converter chain 2015-11-09 11:50:18 -08:00
Howard Mao cb0c2df051 update fpga-zynq 2015-11-05 10:50:13 -08:00
Howard Mao 42e7067400 bump uncore 2015-11-05 10:49:25 -08:00
Howard Mao bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Howard Mao fb501e75c0 fixes for sub-block TL requests in uncore 2015-11-05 10:48:32 -08:00
Howard Mao 7b252d8f89 get rid of now-unnecessary bits in MIF tag 2015-11-05 10:48:32 -08:00
Howard Mao ba5a6af05c correctly stripe data across memory channels in simulation 2015-11-05 10:48:32 -08:00