riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao
4f06a5ff6b add memtest config for testing memory channel mux 2016-03-31 18:41:56 -07:00
Howard Mao
5a74a9b1e7 switch memory interconnect from AXI to TileLink 2016-03-31 18:18:30 -07:00
Howard Mao
3083bbca21 fix TileLink arbiters and add memory interconnect and memory selector 2016-03-31 18:15:51 -07:00
Henry Cook
54dd82ff76 bugfix for WB data buffer 2016-03-31 17:53:49 -07:00
Christopher Celio
1792d01ce1 fix leaky assert in nbdcache 
Squash of #33.
 2016-03-31 15:56:14 -07:00
Howard Mao
6d5c98da7d point submodule pointer to proper commit hash 2016-03-31 15:03:33 -07:00
Howard Mao
7c3b57b8fa switch MMIO network to TileLink 2016-03-31 14:30:10 -07:00
Matthew Naylor
6d3bba6cff Tweaks to README.md 
Remove occurrences of ../scripts/ and instead state that it must be in
your PATH.  Also drop the content introducing the isit script as
tracegen+check.sh subsumes this.
 2016-03-31 14:22:09 -07:00
mwachs5
22e7b3ff2f Update README.md 
- adding instructions of how to run with groundtest
- correct some MD syntax in README
- add some spaces
- minor changes to wording
- remove spurious 'class'
- add commands for running w/ TraceGenConfig
- add code from http://www.cl.cam.ac.uk/~mn416/tracegen.html
- Update README.md
- add WSO note
- correct some syntax within the code blocks and add note about run-asm-tests, run-bmark-tests
- Add one more command to the "quick reference" to show the complete flow
- Correct WSO to WMO
- Add information about tracegen+check.sh
- Use tracegen.py commands instead of running the emulator directly
- added a missing newline
- remove extra head command
 2016-03-31 14:20:14 -07:00
Howard Mao
cf363b1fe4 add TileLink interconnect generator 2016-03-31 14:12:55 -07:00
Andrew Waterman
adb7eacf6e Fix Chisel3 build for XLen=32 2016-03-30 22:48:51 -07:00
Andrew Waterman
70664bbca0 Fix Chisel3 build for UseVM=false 2016-03-30 22:48:31 -07:00
Howard Mao
ab540d536a bump uncore for split metadata chisel3 fix 2016-03-30 22:11:45 -07:00
Howard Mao
d78066db5c chisel3 fix for split metadata 2016-03-30 22:11:19 -07:00
Howard Mao
c831a0a4e5 use scala firrtl instead of stanza firrtl 2016-03-30 19:35:25 -07:00
Howard Mao
be612e3843 bump rocket and uncore 2016-03-30 19:23:19 -07:00
Howard Mao
3d990bdbef workaround for Chisel3 name-aliasing issue 2016-03-30 19:15:22 -07:00
Howard Mao
c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter" 
This reverts commit 5378f79b50.
 2016-03-30 19:06:32 -07:00
Howard Mao
e77900f540 Revert "switch back to Chisel2 for verilog build for now" 
This reverts commit 3673365b08.
 2016-03-30 19:00:38 -07:00
Howard Mao
8e601f26e1 switch back to the correct chisel3 and firrtl branches 2016-03-30 18:59:33 -07:00
Andrew Waterman
8ad8e8a691 Add partial Sv48/Sv57 support 
Right now, we don't support Sv39 and Sv48 at the same time, which needs
to change.
 2016-03-30 11:02:22 -07:00
Howard Mao
1e03408323 get rid of mt benchmark suite 2016-03-29 20:16:07 -07:00
Howard Mao
cf716fea58 fix mm_dramsim2 2016-03-29 20:16:07 -07:00
Howard Mao
3673365b08 switch back to Chisel2 for verilog build for now 2016-03-29 20:16:07 -07:00
Howard Mao
265a82427e add DefaultL2Config and DualCoreConfig to travis 2016-03-29 20:16:07 -07:00
Howard Mao
ad93e0226d Changes to prepare for switch to TileLink interconnect 
We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.

* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
 2016-03-29 20:16:07 -07:00
jackkoenig
5378f79b50 Bump chisel3 and firrtl, add support for firrtl $ delimiter 2016-03-29 20:16:07 -07:00
Howard Mao
38649bd4c1 some edits to groundtest regression tests 2016-03-29 20:16:07 -07:00
Howard Mao
9b9c662952 fix w_last wire 2016-03-29 20:16:07 -07:00
Howard Mao
2b61f28356 don't test DMA controller for now 2016-03-29 20:16:07 -07:00
Howard Mao
e1a03cc9ac fix issue with partial writemasks 2016-03-29 20:16:07 -07:00
Andrew Waterman
e652821962 Use correct kind of TileLink arbiter 
It was "correct" before, but broke Chisel3 build.
 2016-03-28 22:53:47 -07:00
Howard Mao
015992bc9e no longer need MIFMasterTagBits 2016-03-28 12:24:11 -07:00
Howard Mao
8e7f18084b switch RTC to use TileLink instead of AXI 2016-03-28 12:23:16 -07:00
Howard Mao
34852e406d fix bug in NastiRouter 2016-03-28 12:22:43 -07:00
Andrew Waterman
5ce3527b88 Merge pull request #32 from ucb-bar/pr-btb-masking 
separate btb response mask from the frontend mask
 2016-03-26 18:15:14 -07:00
Christopher Celio
f526d380fd separate btb response mask from the frontend mask 
It is now the job of the pipeline to monitor the frontend's valid mask (of
instructions) and the BTB's suggested valid mask (based on the prediction it
makes). Some processors may want to ignore or override the BTB's prediction and
thus can supply their own instruction mask.
 2016-03-26 05:37:26 -07:00
Andrew Waterman
ed280fb3de Remove empty when statement (???) 2016-03-25 15:52:18 -07:00
Andrew Waterman
1ae6d09751 Slightly ameliorate D$->I$ critical path via scoreboard 2016-03-25 15:29:32 -07:00
Andrew Waterman
6c48dc3471 Use more sensible knob values for SmallConfig 2016-03-25 14:18:24 -07:00
Andrew Waterman
cce89f5fbc Bump rocket 2016-03-25 14:18:15 -07:00
Andrew Waterman
a4685a073f Don't instantiate PTW when UseVM=false 2016-03-25 14:17:25 -07:00
Andrew Waterman
27b3cca046 Discover D$, PTW port counts dynamically 
This is a generator, after all...
 2016-03-25 14:16:56 -07:00
Howard Mao
af3bc1cb79 don't use ROM for partial writemask regression 2016-03-25 14:06:06 -07:00
Howard Mao
5372f181b1 add in missing connections for regression test 2016-03-25 14:05:52 -07:00
Howard Mao
7f8f138d6a fix addPendingBitWhenPartialWritemask 2016-03-24 20:01:50 -07:00
Howard Mao
11bd15432a fix bug in RTC 2016-03-24 20:01:50 -07:00
Howard Mao
00b3908d92 git rid of reorder queue in narrower 2016-03-24 20:01:50 -07:00
Andrew Waterman
8d1ba4d1ec Remove hard-coded XLEN values from D$ 2016-03-24 14:52:12 -07:00
Andrew Waterman
d1639416cb Merge pull request #77 from ucb-bar/chisel3 
Preliminary Chisel 3 Support
 2016-03-24 12:56:36 -07:00