Andrew Waterman
65b8340cea
Mitigate D$ hit -> branch -> NPC critical path
2013-11-24 14:21:03 -08:00
Stephen Twigg
3532ae0b79
From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator).
2013-09-24 10:54:09 -07:00
Andrew Waterman
1d2f4f8437
New ISA encoding, AUIPC semantics
2013-09-21 06:32:40 -07:00
Andrew Waterman
f12bbc1e43
working RoCC AccumulatorExample
2013-09-14 22:34:53 -07:00
Andrew Waterman
a0cb711451
Start adding RoCC
2013-09-14 15:31:50 -07:00
Andrew Waterman
d053bdc89f
Remove Hwacha from Rocket
...
Soon it will use the coprocessor interface.
2013-09-12 22:34:38 -07:00
Andrew Waterman
59f5358435
Implement AQ/RL; move fence logic out of cache
2013-09-12 16:07:30 -07:00
Andrew Waterman
243c4ae342
sync up rocket with new isa
2013-09-12 03:44:38 -07:00
Andrew Waterman
d1b5076fee
Don't update BTB when garbage was fetched
2013-08-24 14:44:11 -07:00
Andrew Waterman
52e31f3298
Bypass scoreboard updates
...
This reduces div/mul/D$ miss latency by 1 cycle.
2013-08-24 14:44:04 -07:00
Andrew Waterman
d4a0db4575
Reflect ISA changes
2013-08-24 14:43:55 -07:00
Henry Cook
3a266cbbfa
final Reg changes
2013-08-15 15:28:15 -07:00
Henry Cook
b570435847
Reg standardization
2013-08-13 17:50:02 -07:00
Henry Cook
1a9e43aa11
initial attempt at upgrade
2013-08-12 10:39:11 -07:00
Henry Cook
9abdf4e154
Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
2013-07-23 20:27:58 -07:00
Yunsup Lee
c837c1d800
fix bug in previous JALR commit
...
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
2013-05-21 18:28:44 -07:00
Andrew Waterman
28f914c3f2
don't JALR to speculatively-bypassed addresses
...
Technically not necessary, but probably improves performance.
2013-05-21 16:56:58 -07:00
Andrew Waterman
3a1b5f01b2
don't take interrupts while they're disabled!
...
a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
2013-05-19 23:27:47 -07:00
Andrew Waterman
50ccc20bf3
replace RDNPC with AUIPC
2013-04-22 04:20:15 -07:00
Andrew Waterman
8cbdeb2abf
add LR/SC support
2013-04-04 17:07:09 -07:00
Andrew Waterman
fc46daecf6
don't flush pipeline on writes to side-effect-free PCRs
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notably, K0, K1, and EPC
2013-04-04 17:07:09 -07:00
Andrew Waterman
d4a3351cfc
expose pending interrupts in status register
2013-04-04 17:07:08 -07:00
Andrew Waterman
575bd3445a
re-generalize scoreboard
2013-01-24 18:00:39 -08:00
Rimas Avizienis
63060bc0a8
minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
2013-01-23 19:27:53 -08:00
Henry Cook
e1225c5114
standardize IO naming convention
2013-01-07 13:41:36 -08:00
Andrew Waterman
05f19b21d0
merge multiplier and divider
2012-12-12 02:22:47 -08:00
Andrew Waterman
9c857b83f0
refactor PCR file
2012-11-27 01:28:06 -08:00
Andrew Waterman
352bb464b5
clock gate X/M and M/W store data registers
2012-11-26 20:33:41 -08:00
Andrew Waterman
de2f28193a
get rid of more global constants
2012-11-25 04:24:25 -08:00
Andrew Waterman
c036cdc1ea
add option for 2-cycle load-use delay
2012-11-24 22:01:08 -08:00
Andrew Waterman
29bc361d6c
remove global constants; disentangle hwacha a bit
2012-11-17 17:24:08 -08:00
Andrew Waterman
5a7777fe4d
clock gate integer datapath more aggressively
2012-11-17 06:48:44 -08:00
Andrew Waterman
8dce89703a
new D$ with better QoR and AMO pipelining
...
Vector unit is disabled because nack handling needs to be fixed.
2012-11-16 02:39:33 -08:00
Andrew Waterman
ff8c736d94
move icache invalidate out of request bundle
2012-11-16 01:55:45 -08:00
Yunsup Lee
be1980dd2d
refactored vector queue interface
2012-11-07 01:15:33 -08:00
Andrew Waterman
4d1ca8ba3a
remove more global consts; refactor DTLBs
...
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
2012-11-06 08:13:44 -08:00
Andrew Waterman
e76892f758
remove more global constants
2012-11-06 02:55:45 -08:00
Andrew Waterman
c5b93798fb
factor out more global constants
2012-11-05 23:52:32 -08:00
Andrew Waterman
5b20ed71be
move rd=0 check into bypass logic
...
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
2012-11-05 01:30:57 -08:00
Andrew Waterman
7380c9fe60
aggressively clock gate int and fp datapaths
2012-11-04 16:40:14 -08:00
Henry Cook
88ac5af181
Merged consts-as-traits
2012-10-16 16:32:35 -07:00
Andrew Waterman
197154c485
use BTB for JALR
2012-10-16 02:24:37 -07:00
Andrew Waterman
661f8e635b
merge I$, ITLB, BTB into Frontend
2012-10-16 02:24:37 -07:00
Henry Cook
dfdfddebe8
constants as traits
2012-10-07 22:20:03 -07:00
Henry Cook
b5ff436092
decode constant object split into multiple objects
2012-10-05 15:50:42 -07:00
Andrew Waterman
4e44ed7400
allow back pressure on IPI requests
2012-07-17 22:55:40 -07:00
Huy Vo
fd95159837
INPUT/OUTPUT orderring swapped
2012-07-12 18:16:57 -07:00
Huy Vo
c975c21e44
views removed
2012-06-06 12:51:26 -07:00
Huy Vo
7408c9ab69
removing wires
2012-05-24 10:42:39 -07:00
Andrew Waterman
faee45bf4c
fix setpcr/clearpcr not writing rd
2012-05-21 07:25:35 -07:00
Gage W Eads
d0bc995c88
Fixed IRQ_IPI -> IRQ_TIMER typo
2012-05-14 22:25:12 -07:00
Henry Cook
622a801bb1
Refactored cpu/cache interface to use nested bundles
2012-05-02 11:54:28 -07:00
Andrew Waterman
65ff397122
improved instruction decoding
...
it now makes use of don't-cares by performing logic minimization
2012-05-01 20:16:36 -07:00
Huy Vo
c9c3bd02bc
kill mem stage if fpu nacks in mem stage
2012-04-01 17:02:32 -07:00
Andrew Waterman
7f254d9670
refine FP bugfixes
2012-04-01 14:52:33 -07:00
Huy Vo
c7c35322c2
two bug fixes to fpu
2012-03-31 22:23:51 -07:00
Andrew Waterman
452876af37
fence on vvcfg; implement fence.v.g correctly
2012-03-27 14:49:00 -07:00
Andrew Waterman
54fa6f660d
new supervisor mode
2012-03-24 13:03:31 -07:00
Yunsup Lee
aaed0241af
get rid of vxcptwait
2012-03-21 15:09:04 -07:00
Yunsup Lee
023734175d
now fence stalls in decode
2012-03-20 17:10:05 -07:00
Yunsup Lee
e450e3aa40
fix irt counter bug regarding vector stuff
2012-03-20 17:09:54 -07:00
Yunsup Lee
c036fff79c
fix id interrupt signal
2012-03-19 15:13:57 -07:00
Yunsup Lee
264732556f
fixes to match verilog X semantics
2012-03-19 03:10:00 -07:00
Andrew Waterman
bd27d0fab2
can now take interrupts on stalled instructions
2012-03-19 01:02:06 -07:00
Andrew Waterman
c4a91303fb
update vector fence names and encoding
2012-03-18 20:42:38 -07:00
Yunsup Lee
b793d63182
no vector interrupt masking
2012-03-17 23:01:06 -07:00
Yunsup Lee
b19d783fbd
add vector irq handler
2012-03-14 14:15:28 -07:00
Yunsup Lee
040d62f372
refactored vector exception handling interface
2012-03-13 23:45:34 -07:00
Yunsup Lee
5655dbd5da
add vvcfg and vtcfg instructions
2012-03-13 23:45:34 -07:00
Yunsup Lee
1ba5e7b865
changes to the vector exception interface
2012-03-11 21:38:47 -07:00
Yunsup Lee
e42a4c767e
don't stall on vector fences, keep replaying
2012-03-11 16:29:19 -07:00
Yunsup Lee
44ff22a26f
vector exception handler now handles prefetches correctly
2012-03-10 12:54:36 -08:00
Andrew Waterman
85504f0ddc
fix bug in fence.i and improve test
2012-03-09 03:26:05 -08:00
Yunsup Lee
8acbe98f53
change how fence.*.cv works, now control processor stalls on the fence instruction
2012-03-08 23:32:31 -08:00
Yunsup Lee
e28a551368
refactor code related to vector exceptions
...
- revisied interfaces
- new instructions
2012-03-03 15:15:00 -08:00
Yunsup Lee
8678b3d70c
clean up ioDecoupled/ioPipe interface
2012-03-01 20:48:46 -08:00
Yunsup Lee
c7b01230f4
fix mul/div when waddr=0, can't believe torture didn't find this one
2012-03-01 10:15:27 -08:00
Andrew Waterman
e12b9eae93
remove ext_mem interface
...
hindsight is 20/20
2012-02-26 18:53:39 -08:00
Yunsup Lee
94ba32bbd3
change package name and sbt project name to rocket
2012-02-25 17:09:26 -08:00
Yunsup Lee
a1600d95db
fix bug related to waddr and wdata in wb stage
...
for the instructions which don't use waddr/wdata for writeback, the contents were getting overwritten by the ll ops
it manifested itself after cp imul were sharing the alu with the vu
2012-02-25 12:21:10 -08:00
Yunsup Lee
137fd62007
refactor cpfences
2012-02-25 12:20:36 -08:00
Andrew Waterman
4121fb178c
clean up mul/div interface; use VU mul if HAVE_VEC
2012-02-24 19:22:35 -08:00
Andrew Waterman
b3a3289d34
fix (?) external memory request nack interface
2012-02-24 01:42:33 -08:00
Yunsup Lee
63939efd0c
fix ctrl vec iface hookup - final
2012-02-23 23:03:44 -08:00
Yunsup Lee
bf1e643913
fix ctrl vec iface hookup
2012-02-23 22:55:25 -08:00
Andrew Waterman
6ceaa0e80a
correct and simplify replay_next logic
2012-02-23 16:52:52 -08:00
Andrew Waterman
f939088be1
move datapath control signals into control unit
...
because that's where control signals go
2012-02-23 16:52:52 -08:00
Andrew Waterman
7c929afe2b
HTIF now controls CPU reset
2012-02-22 19:30:03 -08:00
Andrew Waterman
7034c9be65
new htif protocol and implementation
...
You must update your fesvr and isasim!
2012-02-19 23:15:45 -08:00
Andrew Waterman
8b3b3abd3d
fix external memory request nack logic
2012-02-15 18:57:40 -08:00
Andrew Waterman
fe2c1d1321
add vec->ctrl fences
2012-02-15 18:31:19 -08:00
Yunsup Lee
82cd3625c2
add in vackq interface
2012-02-15 17:53:24 -08:00
Andrew Waterman
c13524ad3a
fix vcmdq full replay logic
2012-02-15 17:49:12 -08:00
Yunsup Lee
258d050e1b
add stall logic for vector command queues
2012-02-15 14:48:41 -08:00
Yunsup Lee
32bdf5098a
refactor vector control logic & datapath in the rocket core
2012-02-15 13:30:22 -08:00
Yunsup Lee
7c11c1406c
vector-vector add working!
2012-02-15 02:28:07 -08:00
Andrew Waterman
0ec7767c13
declaring success on FPU for now
2012-02-14 19:11:57 -08:00
Andrew Waterman
297223a13c
squash subsequent external mem request after nack
2012-02-14 15:12:16 -08:00
Andrew Waterman
15dc2d8c40
add fp writeback arbitration logic
2012-02-14 00:32:25 -08:00
Andrew Waterman
0366465cb1
parameterize the scoreboards
2012-02-13 18:12:23 -08:00
