riscv/rocket-chip
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fix id interrupt signal

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This commit is contained in:
Yunsup Lee 2012-03-19 15:13:57 -07:00
parent 0edea00166
commit c036fff79c
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/ctrl.scala
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@ -458,7 +458,7 @@ class rocketCtrl extends Component
val p_irq_timer = (io.dpath.status(15).toBool && io.dpath.irq_timer);
val p_irq_ipi = (io.dpath.status(13).toBool && io.dpath.irq_ipi);
val id_interrupt =
io.dpath.status(SR_ET).toBool && mem_reg_valid &&
io.dpath.status(SR_ET).toBool &&
((io.dpath.status(15).toBool && io.dpath.irq_timer) ||
(io.dpath.status(13).toBool && io.dpath.irq_ipi) ||
vec_irq);