riscv/rocket-chip
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add vector irq handler

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This commit is contained in:
Yunsup Lee 2012-03-14 14:15:28 -07:00
parent 040d62f372
commit b19d783fbd
7 changed files with 38 additions and 2 deletions
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1
rocket/src/main/scala/consts.scala
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@ -143,6 +143,7 @@ object Constants
val PCR_FROMHOST = UFix(17, 5);
val PCR_VECBANK = UFix(18, 5);
val PCR_VECCFG = UFix(19, 5);
val PCR_VECIRQAUX= UFix(20, 5)
// definition of bits in PCR status reg
val SR_ET = 0; // enable traps

5
rocket/src/main/scala/cpu.scala
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@ -201,6 +201,11 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
// fences
ctrl.io.vec_iface.vfence_ready := vu.io.vec_fence_ready
// irqs
ctrl.io.vec_iface.irq := vu.io.irq
ctrl.io.vec_iface.irq_cause := vu.io.irq_cause
dpath.io.vec_iface.irq_aux := vu.io.irq_aux
// exceptions
vu.io.xcpt.exception := ctrl.io.vec_iface.exception
ctrl.io.vec_iface.exception_ack_valid := vu.io.xcpt.exception_ack_valid

13
rocket/src/main/scala/ctrl.scala
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@ -50,6 +50,7 @@ class ioCtrlDpath extends Bundle()
val exception = Bool(OUTPUT);
val cause = UFix(5,OUTPUT);
val badvaddr_wen = Bool(OUTPUT); // high for a load/store access fault
val vec_irq_aux_wen = Bool(OUTPUT)
// inputs from datapath
val xcpt_ma_inst = Bool(INPUT); // high on a misaligned/illegal virtual PC
val btb_hit = Bool(INPUT);
@ -622,6 +623,8 @@ class rocketCtrl extends Component
var vec_replay = Bool(false)
var vec_stalld = Bool(false)
var vec_irq = Bool(false)
var vec_irq_cause = UFix(0,5)
if (HAVE_VEC)
{
// vector control
@ -637,21 +640,26 @@ class rocketCtrl extends Component
vec_replay = vec.io.replay
vec_stalld = vec.io.stalld // || id_vfence_cv && !vec.io.vfence_ready
vec_irq = vec.io.irq
vec_irq_cause = vec.io.irq_cause
}
// exception handling
// FIXME: verify PC in MEM stage points to valid, restartable instruction
val p_irq_timer = (io.dpath.status(15).toBool && io.dpath.irq_timer);
val p_irq_ipi = (io.dpath.status(13).toBool && io.dpath.irq_ipi);
val p_irq_vec = (io.dpath.status(8) && vec_irq)
val interrupt =
io.dpath.status(SR_ET).toBool && mem_reg_valid &&
((io.dpath.status(15).toBool && io.dpath.irq_timer) ||
(io.dpath.status(13).toBool && io.dpath.irq_ipi));
(io.dpath.status(13).toBool && io.dpath.irq_ipi) ||
p_irq_vec);
val interrupt_cause =
Mux(p_irq_ipi, UFix(21,5),
Mux(p_irq_timer, UFix(23,5),
UFix(0,5)));
Mux(p_irq_vec, vec_irq_cause,
UFix(0,5))))
val mem_xcpt_ma_ld = io.dmem.xcpt_ma_ld && !mem_reg_kill
val mem_xcpt_ma_st = io.dmem.xcpt_ma_st && !mem_reg_kill
@ -723,6 +731,7 @@ class rocketCtrl extends Component
io.dpath.exception := wb_reg_exception;
io.dpath.cause := wb_reg_cause;
io.dpath.badvaddr_wen := wb_badvaddr_wen;
io.dpath.vec_irq_aux_wen := wb_reg_exception && wb_reg_cause >= UFix(24)
io.dpath.sel_pc :=
Mux(wb_reg_exception, PC_EVEC, // exception

7
rocket/src/main/scala/ctrl_vec.scala
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@ -43,6 +43,9 @@ class ioCtrlVecInterface extends Bundle
val vximm2q_user_ready = Bool(INPUT)
val vfence_ready = Bool(INPUT)
val irq = Bool(INPUT)
val irq_cause = UFix(5, INPUT)
val exception = Bool(OUTPUT)
val exception_ack_valid = Bool(INPUT)
val exception_ack_ready = Bool(OUTPUT)
@ -63,6 +66,8 @@ class ioCtrlVec extends Bundle
val replay = Bool(OUTPUT)
val stalld = Bool(OUTPUT)
val vfence_ready = Bool(OUTPUT)
val irq = Bool(OUTPUT)
val irq_cause = UFix(5, OUTPUT)
}
class rocketCtrlVec extends Component
@ -235,4 +240,6 @@ class rocketCtrlVec extends Component
io.stalld := reg_xcptwait
io.vfence_ready := !io.sr_ev || io.iface.vfence_ready
io.irq := io.iface.irq
io.irq_cause := io.iface.irq_cause
}

3
rocket/src/main/scala/dpath.scala
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@ -384,6 +384,7 @@ class rocketDpath extends Component
vec.io.wdata := wb_reg_vec_wdata
vec.io.rs2 := wb_reg_rs2
pcr.io.vec_irq_aux := vec.io.irq_aux
pcr.io.vec_appvl := vec.io.appvl
pcr.io.vec_nxregs := vec.io.nxregs
pcr.io.vec_nfregs := vec.io.nfregs
@ -395,6 +396,7 @@ class rocketDpath extends Component
}
else
{
pcr.io.vec_irq_aux := UFix(0)
pcr.io.vec_appvl := UFix(0)
pcr.io.vec_nxregs := UFix(0)
pcr.io.vec_nfregs := UFix(0)
@ -429,4 +431,5 @@ class rocketDpath extends Component
pcr.io.cause := io.ctrl.cause;
pcr.io.pc := wb_reg_pc;
pcr.io.badvaddr_wen := io.ctrl.badvaddr_wen;
pcr.io.vec_irq_aux_wen := io.ctrl.vec_irq_aux_wen
}

8
rocket/src/main/scala/dpath_util.scala
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@ -70,6 +70,8 @@ class ioDpathPCR extends Bundle()
val exception = Bool(INPUT);
val cause = UFix(5, INPUT);
val badvaddr_wen = Bool(INPUT);
val vec_irq_aux = Bits(64, INPUT)
val vec_irq_aux_wen = Bool(INPUT)
val pc = UFix(VADDR_BITS+1, INPUT);
val eret = Bool(INPUT);
val ei = Bool(INPUT);
@ -100,6 +102,7 @@ class rocketDpathPCR extends Component
val reg_k1 = Reg() { Bits() };
val reg_ptbr = Reg() { UFix() };
val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8))
val reg_vec_irq_aux = Reg() { Bits() }
val reg_error_mode = Reg(resetVal = Bool(false));
val reg_status_vm = Reg(resetVal = Bool(false));
@ -145,6 +148,9 @@ class rocketDpathPCR extends Component
when (io.badvaddr_wen) {
reg_badvaddr := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
}
when (io.vec_irq_aux_wen) {
reg_vec_irq_aux := io.vec_irq_aux
}
when (io.exception) {
when (!reg_status_et) {
@ -207,6 +213,7 @@ class rocketDpathPCR extends Component
when (waddr === PCR_K1) { reg_k1 := wdata; }
when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
when (waddr === PCR_VECBANK) { reg_vecbank := wdata(7,0) }
when (waddr === PCR_VECIRQAUX) { reg_vec_irq_aux := wdata }
}
rdata := Bits(0, 64)
@ -227,6 +234,7 @@ class rocketDpathPCR extends Component
is (PCR_PTBR) { rdata := Cat(Bits(0,64-PADDR_BITS), reg_ptbr); }
is (PCR_VECBANK) { rdata := Cat(Bits(0, 56), reg_vecbank) }
is (PCR_VECCFG) { rdata := Cat(Bits(0, 40), io.vec_nfregs, io.vec_nxregs, io.vec_appvl) }
is (PCR_VECIRQAUX){ rdata := reg_vec_irq_aux }
}
}
}

3
rocket/src/main/scala/dpath_vec.scala
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@ -13,6 +13,7 @@ class ioDpathVecInterface extends Bundle
val vximm2q_bits = Bits(SZ_VSTRIDE, OUTPUT)
val vcntq_bits = Bits(SZ_VLEN, OUTPUT)
val evac_addr = Bits(64, OUTPUT)
val irq_aux = Bits(64, INPUT)
}
class ioDpathVec extends Bundle
@ -28,6 +29,7 @@ class ioDpathVec extends Bundle
val wdata = Bits(64, INPUT)
val rs2 = Bits(64, INPUT)
val wen = Bool(OUTPUT)
val irq_aux = Bits(64, OUTPUT)
val appvl = UFix(12, OUTPUT)
val nxregs = UFix(6, OUTPUT)
val nfregs = UFix(6, OUTPUT)
@ -131,6 +133,7 @@ class rocketDpathVec extends Component
}
io.wen := io.valid && io.ctrl.wen
io.irq_aux := io.iface.irq_aux
io.appvl := Mux(io.ctrl.fn === VEC_VL || io.ctrl.fn === VEC_CFGVL, appvl, reg_appvl)
io.nxregs := reg_nxregs
io.nfregs := reg_nfregs