fix bug in previous JALR commit
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
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@ -521,9 +521,9 @@ class Control(implicit conf: RocketConfiguration) extends Component
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val replay_ex_other = wb_dcache_miss && ex_reg_load_use || mem_reg_replay_next
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val replay_ex = replay_ex_structural || replay_ex_other
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ctrl_killx := take_pc_wb || replay_ex
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val take_pc_ex = !Mux(ex_reg_jalr,
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ex_reg_btb_hit && io.dpath.jalr_eq && !replay_ex_other,
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ex_reg_btb_hit === io.dpath.ex_br_taken)
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val take_pc_ex = Mux(ex_reg_jalr,
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!(ex_reg_btb_hit && io.dpath.jalr_eq) && !replay_ex_other,
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ex_reg_btb_hit != io.dpath.ex_br_taken)
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// detect 2-cycle load-use delay for LB/LH/SC
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val ex_slow_bypass = ex_reg_mem_cmd === M_XSC || AVec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_reg_mem_type)
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