riscv/rocket-chip
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refactor cpfences

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This commit is contained in:
Yunsup Lee 2012-02-25 12:20:36 -08:00
parent 4121fb178c
commit 137fd62007
2 changed files with 15 additions and 24 deletions
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27
rocket/src/main/scala/ctrl.scala
View File

@ -600,32 +600,13 @@ class rocketCtrl extends Component
val vec = new rocketCtrlVec()
io.vec_dpath <> vec.io.dpath
io.vec_iface <> vec.io.iface
io.vec_iface.vcmdq_valid := vec.io.iface.vcmdq_valid
io.vec_iface.vximm1q_valid := vec.io.iface.vximm1q_valid
io.vec_iface.vximm2q_valid := vec.io.iface.vximm2q_valid
vec.io.iface.vcmdq_ready := io.vec_iface.vcmdq_ready
vec.io.iface.vximm1q_ready := io.vec_iface.vximm1q_ready
vec.io.iface.vximm2q_ready := io.vec_iface.vximm2q_ready
io.vec_iface.vpfcmdq_valid := vec.io.iface.vpfcmdq_valid
io.vec_iface.vpfximm1q_valid := vec.io.iface.vpfximm1q_valid
io.vec_iface.vpfximm2q_valid := vec.io.iface.vpfximm2q_valid
vec.io.iface.vpfcmdq_ready := io.vec_iface.vpfcmdq_ready
vec.io.iface.vpfximm1q_ready := io.vec_iface.vpfximm1q_ready
vec.io.iface.vpfximm2q_ready := io.vec_iface.vpfximm2q_ready
vec.io.sr_ev := io.dpath.status(SR_EV)
vec.io.exception := wb_reg_exception
vec_replay = vec.io.replay
vec_cpfence = Reg(resetVal = Bool(false))
when (vec.io.cpfence) {
vec_cpfence := Bool(true)
}
when (io.vec_iface.vackq_valid || wb_reg_exception) {
vec_cpfence := Bool(false)
}
io.vec_iface.vackq_ready := Bool(true)
vec.io.sr_ev := io.dpath.status(SR_EV)
vec_cpfence = vec.io.cpfence
}
// exception handling

12
rocket/src/main/scala/ctrl_vec.scala
View File

@ -41,6 +41,7 @@ class ioCtrlVec extends Bundle
val dpath = new ioCtrlDpathVec()
val iface = new ioCtrlVecInterface()
val sr_ev = Bool(INPUT)
val exception = Bool(INPUT)
val replay = Bool(OUTPUT)
val cpfence = Bool(OUTPUT)
}
@ -151,6 +152,8 @@ class rocketCtrlVec extends Component
mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready &&
mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && wb_vec_pfximm2q_enq
io.iface.vackq_ready := Bool(true)
io.replay := valid_common && (
wb_vec_cmdq_enq && !io.iface.vcmdq_ready ||
wb_vec_ximm1q_enq && !io.iface.vximm1q_ready ||
@ -159,5 +162,12 @@ class rocketCtrlVec extends Component
wb_vec_pfximm1q_enq && !io.iface.vpfximm1q_ready ||
wb_vec_pfximm2q_enq && !io.iface.vpfximm2q_ready
)
io.cpfence := valid_common && wb_vec_cpfence && !io.replay
val reg_cpfence = Reg(resetVal = Bool(false))
val do_cpfence = valid_common && wb_vec_cpfence && !io.replay
when (do_cpfence) { reg_cpfence := Bool(true) }
when (io.iface.vackq_valid || io.exception) { reg_cpfence := Bool(false) }
io.cpfence := reg_cpfence
}