Howard Mao
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65b62a9e5f
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unbreak the emulator
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2016-06-08 15:38:39 -07:00 |
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Howard Mao
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40ab0a7960
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fix TL width adapter and make it easier to switch inner data width
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2016-06-08 15:38:39 -07:00 |
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Howard Mao
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a809a1712a
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make sure clocks and reset signals get intialized properly
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2016-06-08 15:38:39 -07:00 |
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Albert Ou
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5151570894
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Fix valid signal for multibeat grants
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2016-06-08 15:13:39 -07:00 |
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Howard Mao
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0969be8804
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Revert "make sure SlowIO clock divider is initialized on reset"
This reverts commit 546aaad8cfb03e45e068733c2b694232bcf9dcdb.
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2016-06-08 13:45:30 -07:00 |
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Howard Mao
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636a46c052
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make sure SlowIO clock divider is initialized on reset
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2016-06-08 10:02:21 -07:00 |
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Howard Mao
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f421e2ab11
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fix TileLinkWidthAdapter
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2016-06-08 09:58:23 -07:00 |
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Donggyu Kim
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99b257316e
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replace emulator with verilator for chisel3
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2016-06-08 02:43:54 -07:00 |
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Howard Mao
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08e53a00f0
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bump cde for better match failure stack trace
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2016-06-07 16:15:10 -07:00 |
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Howard Mao
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2cd897e240
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Revert "include the unmatched field in CDEMatchError"
This reverts commit ff2937a788.
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2016-06-07 16:13:01 -07:00 |
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Wesley W. Terpstra
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324cabc494
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tilelink: wmask was double the width it should be
When amo_offset = UInt(0), UIntToOH(amo_offset) = "b01", not b"1".
This meant that the amo wmask was double wide, making wmask() fat.
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2016-06-07 14:04:01 -07:00 |
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Howard Mao
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8db27a36c4
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fix Tile reset power on behavior
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2016-06-07 11:06:38 -07:00 |
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Palmer Dabbelt
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e6c4372332
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Fix "make run-asm-tests" for Chisel 3
This was just a missing Makefrag-verilog dependency (the .d file).
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2016-06-06 21:36:55 -07:00 |
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Andrew Waterman
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2c17f828b6
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bump chisel and rocket
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2016-06-06 21:36:51 -07:00 |
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Wesley W. Terpstra
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5495705acf
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Configs: enable AHB for FPGAs
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2016-06-06 21:36:09 -07:00 |
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Wesley W. Terpstra
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ef27cc3a33
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RocketChip: handle atomics only if needed
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2016-06-06 21:36:03 -07:00 |
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Wesley W. Terpstra
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3e0ec855cf
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RocketChip: add ahb mem interface
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2016-06-06 21:35:59 -07:00 |
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Wesley W. Terpstra
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d2b505f2d2
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RocketChip: rename mem to mem_axi in preparation for new bus type
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2016-06-06 21:35:55 -07:00 |
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Wesley W. Terpstra
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2086c0d603
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Configs: add a parameter to control the memory subsystem interface
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2016-06-06 21:35:43 -07:00 |
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Wesley W. Terpstra
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2ddada1732
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ahb: add mmio_ahb option
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2016-06-06 21:35:39 -07:00 |
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Wesley W. Terpstra
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31f1dcaf84
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ahb: rename mmio outputs to mmio_axi
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2016-06-06 21:35:34 -07:00 |
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Wesley W. Terpstra
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7a24527448
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ahb: make MMIO channels specifiy bus type (we will have more than one bridge)
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2016-06-06 21:35:30 -07:00 |
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Wesley W. Terpstra
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f3a557b67b
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ahb: AHB parameters should be site specific
Conflicts:
src/main/scala/Configs.scala
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2016-06-06 21:35:24 -07:00 |
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Andrew Waterman
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4f2e2480a8
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When exceptions occur in D-mode, set pc=0x808, not 0x800
Closes #43
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2016-06-06 20:57:22 -07:00 |
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Howard Mao
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172c4f25f4
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bump groundtest and uncore
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2016-06-06 17:45:30 -07:00 |
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Howard Mao
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f44778fa56
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make sure Cached generator comparison truncates to correct size
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2016-06-06 17:45:04 -07:00 |
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Howard Mao
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ff2937a788
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include the unmatched field in CDEMatchError
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2016-06-06 11:23:20 -07:00 |
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Howard Mao
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022503748e
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make Memtest generators more configurable
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2016-06-06 09:44:09 -07:00 |
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Howard Mao
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2163ebfca3
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use a generic Nasti memory driver for unit tests
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2016-06-06 09:43:39 -07:00 |
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Howard Mao
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2d66ac93d3
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make sure HastiRAM cuts off the correct number of bits for word address
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2016-06-06 09:26:51 -07:00 |
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Andrew Waterman
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d24c87f8ba
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Update PLIC/PRCI address map (#124)
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2016-06-06 04:51:55 -07:00 |
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Andrew Waterman
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dd85f2410f
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Avoid need for cloneType
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2016-06-05 23:47:56 -07:00 |
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Andrew Waterman
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631e3e2dd9
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Make PRCI a singleton, not per-tile
Some stuff is densely packed in the address space (e.g. IPI regs),
so needs to be on the same TileLink slave port
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2016-06-05 23:06:21 -07:00 |
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Andrew Waterman
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be7500e4a9
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Update PLIC addr map
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2016-06-05 23:04:51 -07:00 |
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Megan Wachs
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b832689642
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Correct Debug ROM contents
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2016-06-05 19:35:25 -07:00 |
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Megan Wachs
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605fb5b92f
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[debug]: fix issue with subword select logic
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2016-06-05 19:31:07 -07:00 |
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Megan Wachs
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3e8322816b
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Correct DMINFO Fields
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2016-06-05 19:29:50 -07:00 |
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Megan Wachs
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7e550ab07c
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[debug] rocket: fix for issue 121, correct debug ROM and stall logic
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2016-06-05 19:29:44 -07:00 |
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Andrew Waterman
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ece3ab9c3d
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Refactor AddrMap and its usage (#122)
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2016-06-03 17:29:05 -07:00 |
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Andrew Waterman
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3b0c1ed0c3
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Cope with changes to AddrMap
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2016-06-03 13:50:29 -07:00 |
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Andrew Waterman
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cf8be98b2b
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Cope with changes to AddrMap
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2016-06-03 13:48:43 -07:00 |
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Andrew Waterman
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2e88ffc364
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Cope with changes to AddrMap
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2016-06-03 13:48:09 -07:00 |
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Andrew Waterman
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28161cab45
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Merge AddrHashMap and AddrMap
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2016-06-03 13:46:53 -07:00 |
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Andrew Waterman
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f1745bf142
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Allow PLIC nPriorities=0 (priority fixed at 1)
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2016-06-02 13:48:29 -07:00 |
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Andrew Waterman
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b7ca2145b3
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Fix PLIC control bug when !grant.ready
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2016-06-02 13:47:59 -07:00 |
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Andrew Waterman
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c8338ad809
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Instantiate Debug Module (#119)
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2016-06-02 10:53:41 -07:00 |
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Andrew Waterman
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0866b4c045
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Can't assign to Vec literals
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2016-06-01 23:36:34 -07:00 |
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Andrew Waterman
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20e1de08da
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Avoid chisel2 pitfall
This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3. D'oh.
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2016-06-01 23:35:49 -07:00 |
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Andrew Waterman
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5629fb62bf
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Avoid bitwise sub-assignment
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2016-06-01 21:59:02 -07:00 |
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Andrew Waterman
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9518b3d589
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Fix arithmetic in ROM row count
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2016-06-01 21:59:02 -07:00 |
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