riscv/rocket-chip
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58 Commits

Author SHA1 Message Date
Colin Schmidt
3e0b5d6fd9 Ensure that a TSHR doesn't see a valid Acquire if that is blocked by a Release, 
but would otherwise be allocated.

Closes #45
 2016-05-20 16:35:30 -07:00
Ken McMillan
fd83d20857 Use a def instead of a lazy val in ManagerCoherenceAgent. 
Prevents C++ emulator from randomizing inputs in unit testing.

Closes #44
 2016-05-20 16:31:12 -07:00
Howard Mao
31e145eaf0 fix BroadcastHub allocation and routing 2016-04-05 16:21:18 -07:00
Henry Cook
93773a4496 Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks. 
To elide several races between reading and writing the metadata array for different types of transactions, all L2XactTrackers can now sink Voluntary Releases (writebacks from the L1 in the current implementation). These writebacks are merged with the ongoing transaction, and the merging tracker supplies an acknowledgment of the writeback in addition to its ongoing activities. This change involved another refactoring of the control logic for allocating new trackers and routing incoming Acquires and Releases. BroadcastHub uses the new routing logic, but still processes all voluntary releases through the VoluntaryReleaseTracker (not a problem because there are no metadata update races).

Closes #18
Closes #20
 2016-03-10 17:14:34 -08:00
Henry Cook
929d8e31f7 refactor ready/valid logic for routing release messages in the l2 2016-02-19 16:30:26 -08:00
Howard Mao
adaec18bec add TL manager for MMIO requests 2016-02-02 12:49:58 -08:00
Howard Mao
4ff1aea288 fix more Chisel3 deprecations 2016-01-14 14:55:45 -08:00
Henry Cook
64aaf71b06 L2AcquireTracker refactor to support merging Gets and Puts into Prefetches of the correct type. 
Transaction metadata for primary and seconday misses now stored in the secondary miss queue.

Added BuiltInAcquireBuilder factory.
 2015-11-16 18:10:09 -08:00
Howard Mao
7942be4e01 make sure outerTL method is idempotent 2015-11-09 11:10:02 -08:00
Henry Cook
f8594da1d3 depend on external cde library 2015-10-21 18:17:17 -07:00
Howard Mao
02d113b39f outerDataBits / innerDataBits should be per beat, not per block 2015-10-21 11:31:13 -07:00
Henry Cook
7fa3eb95e3 refactor tilelink params 2015-10-14 12:13:37 -07:00
Henry Cook
31be6407ec Removed all traces of params 2015-10-14 00:23:28 -07:00
Howard Mao
24f3fac90a fix broadcast hub and TL -> NASTI converter to support subblock operations 2015-09-14 12:56:44 -07:00
Andrew Waterman
05d311c517 Use Vec.apply, not Vec.fill, for type nodes 2015-08-27 09:47:02 -07:00
Henry Cook
005752e2a6 use the parameters used to create the original object 2015-08-10 14:43:17 -07:00
Andrew Waterman
2d6b3b2331 Don't use clone 2015-07-15 18:06:27 -07:00
Andrew Waterman
55059632c4 Temporarily use HTIF to push RTC value to cores 2015-07-05 16:19:39 -07:00
Henry Cook
172c372d3e L2 alloc cleanup 2015-05-12 17:14:06 -07:00
Henry Cook
6d40a61060 TileLink scala doc and parameter renaming 2015-04-19 22:06:44 -07:00
Henry Cook
ba7a8b1752 TileLink refactor; TileLinkPorts now available. L2Banks no longer have unique ids (suitable for hierarhical P&R). 2015-04-17 16:55:20 -07:00
Henry Cook
ce3271aef2 refactor LNClients and LNManagers 2015-04-15 15:48:36 -07:00
Henry Cook
3cf1778c92 moved ecc lib to uncore, l2 checks for partial write masks when ecc is enabled 2015-04-06 12:22:23 -07:00
Henry Cook
9708d25dff Restructure L2 state machine and utilize HeaderlessTileLinkIO 2015-04-06 12:19:51 -07:00
Henry Cook
004ad11af6 cleanup pending signals 2015-03-18 22:14:41 -07:00
Henry Cook
1ff184bf62 first cut at optimized state transitions 2015-03-18 17:55:05 -07:00
Henry Cook
638bace858 avoid reading data when write mask is full 2015-03-17 20:28:21 -07:00
Henry Cook
b08dced37c first cut at pending scoreboarding 2015-03-17 17:51:00 -07:00
Henry Cook
8181262419 clean up incoherent and probe flags 2015-03-12 16:22:14 -07:00
Henry Cook
059575c334 cleanup mergeData and prep for cleaner data_buffer in L2 2015-03-11 15:43:41 -07:00
Henry Cook
1bed6ea498 New metadata-based coherence API 2015-02-28 17:32:03 -08:00
Henry Cook
0c66e70f14 cleanup of conflicts; allocation bugfix 2015-02-06 13:20:44 -08:00
Henry Cook
6141b3efc5 uncached -> builtin_type 2015-02-02 01:02:06 -08:00
Henry Cook
3aa030f960 Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor. 2015-02-01 20:37:16 -08:00
Henry Cook
9ef00d187f %s/master/manager/g + better comments 2014-12-29 22:55:58 -08:00
Henry Cook
e62c71203e disconnect unused outer network headers 2014-12-22 18:50:37 -08:00
Henry Cook
d121af7f94 Simplify release handling 2014-12-18 17:12:29 -08:00
Henry Cook
ab39cbb15d cleanup DirectoryRepresentation and coherence params 2014-12-15 19:24:42 -08:00
Henry Cook
424df2368f 1R/W L2 data array? 
Add TLDataBeats to new LLC; all bmarks pass
 2014-12-12 17:05:21 -08:00
Henry Cook
3026c46a9c Finish adding TLDataBeats to uncore & hub 2014-12-12 17:04:52 -08:00
Henry Cook
cb7e712599 Added uncached write data queue to coherence hub 2014-11-12 12:55:07 -08:00
Henry Cook
82155f333e Major tilelink revision for uncached message types 2014-11-11 17:36:55 -08:00
Henry Cook
10309849b7 Remove master_xact_id from Probe and Release 2014-11-06 12:07:33 -08:00
Henry Cook
82fe22f958 support for multiple tilelink paramerterizations in same design 
Conflicts:

	src/main/scala/cache.scala
 2014-09-24 11:30:40 -07:00
Henry Cook
149d51d644 more coherence API cleanup 2014-09-20 16:57:13 -07:00
Yunsup Lee
0b51d70bd2 add LICENSE 2014-09-12 15:31:38 -07:00
Henry Cook
9ab3a4262c Cache utility traits. Completely compiles, asm tests hang. 2014-08-11 18:35:49 -07:00
Henry Cook
f411fdcce3 Full conversion to params. Compiles but does not elaborate. 2014-08-08 12:21:57 -07:00
Henry Cook
3c329df7e7 refactor Metadata, clean and expand coherence API 2014-05-28 13:35:08 -07:00
Henry Cook
0237229921 client/master -> inner/outer 2014-04-29 16:49:18 -07:00