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3532ae0b79
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From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator).
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2013-09-24 10:54:09 -07:00 |
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db1e09f0d0
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Fix issues with RoCC AccumulatorExample stalls on memory interface
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2013-09-23 00:21:43 -07:00 |
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158cee08af
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Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads)
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2013-09-22 03:18:06 -07:00 |
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1d2f4f8437
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New ISA encoding, AUIPC semantics
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2013-09-21 06:32:40 -07:00 |
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25ab402932
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swap JAL, JALR encodings
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2013-09-15 04:29:06 -07:00 |
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110e53cb48
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Revert "Add early out to multiplier"
This broke recently and I don't have time to figure out why.
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2013-09-15 04:15:32 -07:00 |
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88d1c47665
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don't disassemble within chisel
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2013-09-15 04:14:45 -07:00 |
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f12bbc1e43
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working RoCC AccumulatorExample
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2013-09-14 22:34:53 -07:00 |
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18968dfbc7
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Move store data generation into cache
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2013-09-14 16:15:07 -07:00 |
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a0cb711451
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Start adding RoCC
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2013-09-14 15:31:50 -07:00 |
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d053bdc89f
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Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
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2013-09-12 22:34:38 -07:00 |
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1edb1e2a0a
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Ignore LSB of PC
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2013-09-12 17:55:58 -07:00 |
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59f5358435
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Implement AQ/RL; move fence logic out of cache
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2013-09-12 16:07:30 -07:00 |
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243c4ae342
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sync up rocket with new isa
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2013-09-12 03:44:38 -07:00 |
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95dd0d8be1
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Remove DebugIO/error mode
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2013-09-11 20:15:21 -07:00 |
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f9b85d8158
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NetworkIOs no longer use thunks
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2013-09-10 16:15:19 -07:00 |
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d06e24ac24
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new enum syntax
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2013-09-10 10:51:35 -07:00 |
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cfbfa6b895
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Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.
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2013-09-05 19:22:34 -07:00 |
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d896ccbd43
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Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/htif.scala
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2013-09-05 16:11:53 -07:00 |
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b9f6e1a7ec
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Don't update BTB when garbage was fetched
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2013-08-26 14:53:04 -07:00 |
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44e92edf92
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fix scr parameterization bug
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2013-08-24 22:42:51 -07:00 |
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3895b75a56
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Support non-power-of-2 BTBs; prefer invalid entries
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2013-08-24 17:33:11 -07:00 |
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2ca5127785
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parameterize number of SCRs
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2013-08-24 15:47:14 -07:00 |
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daf23b8f79
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Add early out to multiplier
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2013-08-24 14:44:23 -07:00 |
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67f80ba4b2
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Stall div/mul writeback until WB slot is free
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2013-08-24 14:44:17 -07:00 |
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d1b5076fee
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Don't update BTB when garbage was fetched
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2013-08-24 14:44:11 -07:00 |
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52e31f3298
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Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
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2013-08-24 14:44:04 -07:00 |
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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ff7b486006
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standardized sbt build
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2013-08-15 18:13:19 -07:00 |
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ae02ebd153
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Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
Conflicts:
src/core.scala
src/ctrl.scala
src/dpath_util.scala
src/fpu.scala
src/nbdcache.scala
src/tile.scala
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2013-08-15 16:35:27 -07:00 |
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
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b570435847
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Reg standardization
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2013-08-13 17:50:02 -07:00 |
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858169917e
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removed dummy DNCs handled by pruning
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2013-08-12 22:34:46 -07:00 |
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d9b3c7cfc8
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Moved RenEn to ChiselUtil
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2013-08-12 22:18:25 -07:00 |
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387cf0ebe0
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reset -> resetVal, getReset -> reset
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2013-08-12 20:51:54 -07:00 |
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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de313d97de
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2013-08-02 16:30:09 -07:00 |
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4eaab214d2
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:29:51 -07:00 |
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bef6c1db35
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minor nbdcache cleanup
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2013-08-02 16:29:37 -07:00 |
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3132db4f90
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Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.
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2013-07-30 16:36:28 -07:00 |
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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5c00d0a030
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new tilelink arbiter type
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2013-07-09 15:31:46 -07:00 |
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7cc53c7725
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clean up Str
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2013-06-15 00:45:53 -07:00 |
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95c5147dc5
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Add RISC-V instruction disassembler
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2013-06-13 10:31:04 -07:00 |
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569d8fd796
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Merge branch 'tilelink-data'
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2013-05-23 14:14:40 -07:00 |
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12205b9684
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remove obsolete config file reader prototype
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2013-05-23 14:09:03 -07:00 |
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fe9adfe71b
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Simplify and correct integer multiplier
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2013-05-22 17:27:50 -07:00 |
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11133d6d4c
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clock gate s2 registers in the frontend
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2013-05-21 18:59:21 -07:00 |
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c837c1d800
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fix bug in previous JALR commit
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
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2013-05-21 18:28:44 -07:00 |
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69b508ff39
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ported caches and htif to use new tilelink
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2013-05-21 17:21:04 -07:00 |
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