Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.
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@ -97,6 +97,7 @@ object PCR
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val K1 = 13
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val VECBANK = 18
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val VECCFG = 19
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val STATS = 28
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val RESET = 29
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val TOHOST = 30
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val FROMHOST = 31
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@ -131,6 +132,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component
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val replay = Bool(OUTPUT)
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val vecbank = Bits(OUTPUT, 8)
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val vecbankcnt = UFix(OUTPUT, 4)
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val stats = Bool(OUTPUT)
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val vec_appvl = UFix(INPUT, 12)
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val vec_nxregs = UFix(INPUT, 6)
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val vec_nfregs = UFix(INPUT, 6)
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@ -150,6 +152,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component
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val reg_k1 = Reg{Bits(width = conf.xprlen)}
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val reg_ptbr = Reg{UFix(width = PADDR_BITS)}
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val reg_vecbank = Reg(resetVal = Fix(-1,8).toBits)
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val reg_stats = Reg(resetVal = Bool(false))
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val reg_error_mode = Reg(resetVal = Bool(false))
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val reg_status = Reg{new Status} // reset down below
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@ -193,6 +196,8 @@ class PCR(implicit conf: RocketConfiguration) extends Component
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cnt = cnt + reg_vecbank(i)
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io.vecbankcnt := cnt(3,0)
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io.stats := reg_stats
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when (io.badvaddr_wen || io.vec_irq_aux_wen) {
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val wdata = Mux(io.badvaddr_wen, io.rw.wdata, io.vec_irq_aux)
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val (upper, lower) = Split(wdata, VADDR_BITS)
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@ -240,7 +245,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component
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reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank, read_veccfg,
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reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank/*x*/, read_veccfg/*x*/,
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reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/,
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reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost, reg_fromhost
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reg_stats/*x*/, read_veccfg/*x*/, reg_tohost, reg_fromhost
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)(addr)
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when (wen) {
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@ -267,6 +272,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component
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when (addr === K1) { reg_k1 := wdata; }
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when (addr === PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
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when (addr === VECBANK) { reg_vecbank:= wdata(7,0) }
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when (addr === STATS) { reg_stats := wdata(0) }
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}
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io.host.ipi_rep.ready := Bool(true)
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