Stephen Twigg 158cee08af Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads)

2013-09-22 03:18:06 -07:00

rocket/src/main/scala

Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads)

2013-09-22 03:18:06 -07:00

Description

Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)

13 MiB

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