Howard Mao
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33676e81f8
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use isOneOf as much as possible
|
2016-08-19 09:56:06 -07:00 |
|
Andrew Waterman
|
458520c8f6
|
Use a generic UInt for TileLink op sizes, rather than MT_xx enum
|
2016-08-09 15:24:51 -07:00 |
|
Andrew Waterman
|
5d4f6383f2
|
[rocket] Automatically kill D$ access on address exceptions
Doing this internally to the cache eliminates a long control path
from the cache to the core and back to the cache.
|
2016-08-02 17:20:49 -07:00 |
|
Andrew Waterman
|
832e56d3c7
|
Fix toBits/toUInt/toSInt deprecation warnings
|
2016-07-31 17:13:52 -07:00 |
|
Andrew Waterman
|
8a7fc75b53
|
fix metadata race in blocking L1 DCache
|
2016-07-28 17:54:28 -07:00 |
|
Andrew Waterman
|
d78f1aacd0
|
Clean up some zero-width wire cases using UInt.extract
|
2016-07-14 22:08:01 -07:00 |
|
Andrew Waterman
|
1699622730
|
Don't speculatively refill I$ in uncacheable regions
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2016-07-09 01:10:58 -07:00 |
|
Andrew Waterman
|
25fdabdd59
|
Don't implicitly create Vecs, since they're heavyweight
|
2016-07-06 01:41:31 -07:00 |
|
Howard Mao
|
a9e0a5e2df
|
changes to imports after uncore refactor
|
2016-06-28 14:09:31 -07:00 |
|
Andrew Waterman
|
60bddddfe6
|
Merge sptbr and sasid
|
2016-06-17 18:29:05 -07:00 |
|
Andrew Waterman
|
586c1079d0
|
Fix D$ for set size > page size
|
2016-06-09 13:02:28 -07:00 |
|
Andrew Waterman
|
51379621d6
|
Flush blocking D$ on FENCE.I
|
2016-05-31 19:27:28 -07:00 |
|
Andrew Waterman
|
40f38dde63
|
Work around lack of zero-width wires in D$
|
2016-05-25 19:44:31 -07:00 |
|
Andrew Waterman
|
4605b616c1
|
Fix bug in D$ AMO/storegen logic
|
2016-05-24 16:26:07 -07:00 |
|
Andrew Waterman
|
5dac7b818d
|
Support set associativity in blocking D$
|
2016-05-24 15:45:52 -07:00 |
|
Andrew Waterman
|
e0addb5723
|
Support uncached AMOs in blocking D$
|
2016-05-24 15:45:35 -07:00 |
|
Andrew Waterman
|
3b35c7470e
|
Add uncached support to blocking D$
|
2016-05-24 15:05:41 -07:00 |
|
Andrew Waterman
|
b92c73e361
|
Add LR/SC to blocking D$
|
2016-05-24 15:05:41 -07:00 |
|
Andrew Waterman
|
0d93d1a1a0
|
Clean up pending store logic a bit
|
2016-05-24 15:05:41 -07:00 |
|
Andrew Waterman
|
0b8de578d4
|
Add additional D$ store buffering to prevent structural hazards
|
2016-05-24 15:05:41 -07:00 |
|
Andrew Waterman
|
d7790ac6a4
|
WIP on blocking D$
|
2016-05-24 15:05:41 -07:00 |
|
Andrew Waterman
|
7bc38383de
|
add (non-working) blocking data cache
|
2016-05-20 18:59:05 -07:00 |
|
Andrew Waterman
|
25ecfb9bbc
|
clean up caches
- remove incompatible blocking D$
- remove direct-mapped nonblocking cache
|
2012-02-12 20:32:06 -08:00 |
|
Andrew Waterman
|
725190d0ee
|
update to new chisel
|
2012-02-11 17:20:33 -08:00 |
|
Christopher Celio
|
1be9d15944
|
Fixed bug regarding case sensitivity regarding ioICache,ioDCache
|
2012-02-07 14:07:42 -08:00 |
|
Andrew Waterman
|
a5a020f97b
|
update chisel and remove SRAM_READ_LATENCY
|
2012-01-23 20:59:38 -08:00 |
|
Henry Cook
|
8766438bb9
|
Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
|
2012-01-23 17:09:23 -08:00 |
|
Henry Cook
|
7e25749581
|
Groundwork for assoc cache implementation
|
2012-01-18 17:09:35 -08:00 |
|
Henry Cook
|
1d76255dc1
|
new chisel version jar and find and replace INPUT and OUTPUT
|
2012-01-18 14:39:57 -08:00 |
|
Andrew Waterman
|
ffe23a1ee8
|
fix WAW hazard handling
|
2012-01-02 00:25:11 -08:00 |
|
Andrew Waterman
|
a8d0cd95e6
|
hellacache now works
|
2011-12-17 03:26:11 -08:00 |
|
Andrew Waterman
|
56c4f44c2a
|
hellacache returns!
but AMOs are unimplemented.
|
2011-12-12 06:49:39 -08:00 |
|
Andrew Waterman
|
8308345364
|
work in progress on hellacache
|
2011-12-10 07:01:47 -08:00 |
|
Andrew Waterman
|
ce201559f3
|
Support cache->cpu nacks one cycle after request
|
2011-12-10 00:42:09 -08:00 |
|
Andrew Waterman
|
c01e1f1cef
|
Don't replay from EX stage.
EX replays are now handled from MEM. We may move them to WB.
|
2011-12-09 19:42:58 -08:00 |
|
Andrew Waterman
|
218f63e66e
|
code cleanup/parameterization
|
2011-12-09 00:42:43 -08:00 |
|
Rimas Avizienis
|
fa784d1d7d
|
made setReadLatency argument a parameter defined in consts.scala
|
2011-12-05 00:33:17 -08:00 |
|
Rimas Avizienis
|
ff95cacb55
|
icache/dcache tag+data arrays now implemented using Mem4()
however there seems to be a bug - readLatency needs to be set to 0
for C model to work, and 1 for Verilog model.
|
2011-12-04 01:18:38 -08:00 |
|
Rimas Avizienis
|
e894b79870
|
caches now use Mem4() memories for tag+data arrays
|
2011-12-03 19:41:15 -08:00 |
|
Rimas Avizienis
|
c580180b66
|
tweaks to cache/SRAM interface for TSMC65 SRAMs
|
2011-12-02 02:01:08 -08:00 |
|
Rimas Avizienis
|
cf1965493b
|
renamed SRAM modules to match TSMC65 MC generated SRAMs
|
2011-12-01 13:14:33 -08:00 |
|
Rimas Avizienis
|
c42d8149b7
|
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
|
2011-11-17 23:50:45 -08:00 |
|
Rimas Avizienis
|
80b4253318
|
fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
|
2011-11-16 02:04:28 -08:00 |
|
Rimas Avizienis
|
82a636ff55
|
AMOADD, AMOAND, AMOOR, AMOSWAP working
|
2011-11-15 00:51:45 -08:00 |
|
Rimas Avizienis
|
48cec01710
|
updated riscv-bmarks and riscv-tests to build with new toolchain
|
2011-11-15 00:11:22 -08:00 |
|
Rimas Avizienis
|
9d3471a569
|
more cache fixes, more test harness debug output
|
2011-11-13 23:32:18 -08:00 |
|
Rimas Avizienis
|
67c7e7e28f
|
cache/tlb bugfixes, increased memory size to 256meg
|
2011-11-13 13:06:35 -08:00 |
|
Rimas Avizienis
|
5f4b15b809
|
added ld/st misaligned exceptions
|
2011-11-13 00:03:17 -08:00 |
|
Rimas Avizienis
|
35af912bd2
|
cache optimizations, cleanup, and testharness improvement
|
2011-11-12 22:13:29 -08:00 |
|
Rimas Avizienis
|
91c252ad08
|
fixing output enable signals for data/tag SRAMs
|
2011-11-12 15:47:47 -08:00 |
|