Andrew Waterman
|
137b77d780
|
Merge pull request #4 from ucb-bar/chisel3
Work around Chisel3's lack of 0-width wires
|
2016-03-15 17:30:34 -07:00 |
|
Palmer Dabbelt
|
50f61687de
|
Work around Chisel3's lack of 0-width wires
This is super ugly, but it's necessary to get Chisel3 to compile. Note
that this still fails simulations in Chisel3, so it might be wrong.
|
2016-03-14 22:50:37 -07:00 |
|
Andrew Waterman
|
13dcb96b7f
|
Update TLB interface
n.b. no need to set mprv, since prv = S.
|
2016-03-14 17:55:19 -07:00 |
|
Andrew Waterman
|
3e721fe80b
|
Merge pull request #2 from ucb-bar/chisel3
Pass a BitPat to Lookup
|
2016-03-06 04:27:52 -08:00 |
|
Palmer Dabbelt
|
bf06ba0d37
|
Pass a BitPat to Lookup
This is the only supported type of Lookup in Chisel 3.
|
2016-03-05 18:50:56 -08:00 |
|
Howard Mao
|
c2e9971b5f
|
move toaxe.py script into top-level Rocket-Chip repo
|
2016-02-23 08:52:32 -08:00 |
|
Matthew Naylor
|
1b6871f3d8
|
Add author, affiliation, and sponsor info to trace-generator files.
|
2016-02-23 15:30:11 +00:00 |
|
Howard Mao
|
91e3c9b96f
|
reuse generator parameters for tracegen
|
2016-02-22 09:53:31 -08:00 |
|
Matthew Naylor
|
e63fc3bb44
|
Added trace generator
|
2016-02-22 08:43:34 -08:00 |
|
Howard Mao
|
da302504a5
|
get rid of sequential same id get regression in broadcast regression suite
|
2016-02-19 23:14:34 -08:00 |
|
Howard Mao
|
000af5e662
|
add NastiIOHostIO converter test
|
2016-02-19 11:21:53 -08:00 |
|
Howard Mao
|
f290157cb3
|
check that MultiWidthFifo count is correct
|
2016-02-17 13:36:07 -08:00 |
|
Howard Mao
|
4915a258f6
|
add unit test for some modules
|
2016-02-16 23:10:55 -08:00 |
|
Howard Mao
|
e90dfcb403
|
add test for NASTI to TL converter
|
2016-02-10 11:07:37 -08:00 |
|
Howard Mao
|
428fa14601
|
fix DummyPTW response
|
2016-01-27 15:33:02 -08:00 |
|
Howard Mao
|
a59ff38b67
|
use MMIO for DMA requests instead of separate channel
|
2016-01-27 15:33:02 -08:00 |
|
Howard Mao
|
04e1f8c5c3
|
lowercase SMI to Smi
|
2016-01-11 16:18:49 -08:00 |
|
Howard Mao
|
80d97d5f9e
|
test DMA streaming
|
2016-01-06 21:38:12 -08:00 |
|
Howard Mao
|
b8d0376d3f
|
Merge pull request #1 from ucb-bar/dma
add DMA test
|
2015-12-22 10:33:48 -05:00 |
|
Howard Mao
|
24eecee148
|
add DMA test
|
2015-12-16 21:26:22 -08:00 |
|
Howard Mao
|
4858ca9a60
|
add a regression to test proper writeback
|
2015-12-16 21:05:56 -08:00 |
|
Howard Mao
|
176d3c890c
|
add some more regression tests
|
2015-12-15 23:00:17 -08:00 |
|
Howard Mao
|
484e8ce20b
|
add regression tests for catching specific memory bugs
|
2015-12-06 02:57:45 -08:00 |
|
Howard Mao
|
158d1d870c
|
do all the writes before doing the gets in GeneratorTest
|
2015-11-21 09:42:00 -08:00 |
|
Howard Mao
|
49c6b1ad1c
|
add CacheFillTest
|
2015-11-19 00:15:36 -08:00 |
|
Howard Mao
|
640544ea5a
|
generalize test harness
|
2015-11-18 22:54:05 -08:00 |
|
Howard Mao
|
f325874420
|
make sure timeout doesn't trigger spuriously on reset
|
2015-11-18 22:53:50 -08:00 |
|
Howard Mao
|
8bc90ab9bd
|
separate out common functionality
|
2015-11-18 20:53:19 -08:00 |
|
Howard Mao
|
10f4c6c71c
|
interleave cached and uncached requests
|
2015-11-12 11:34:44 -08:00 |
|
Howard Mao
|
7cae6cedf5
|
finished bit should be set true if generator not being used
|
2015-11-11 18:51:16 -08:00 |
|
Howard Mao
|
f93872d6b4
|
make sure cached generator actually drives finished signal
|
2015-11-11 18:45:36 -08:00 |
|
Howard Mao
|
eeda3dd770
|
add README
|
2015-11-11 18:30:19 -08:00 |
|
Howard Mao
|
9482d944ca
|
make Uncached generator vary the alloc bit
|
2015-11-11 18:26:56 -08:00 |
|
Howard Mao
|
8a6b231b08
|
explicitly configure the number of requests being sent by generators
|
2015-11-11 14:32:19 -08:00 |
|
Howard Mao
|
13f62e0364
|
make sure generators can detect lockup
|
2015-11-10 14:39:56 -08:00 |
|
Howard Mao
|
520925c207
|
fix up build.sbt and add gitignore
|
2015-11-10 13:38:39 -08:00 |
|
Howard Mao
|
d844bee310
|
properly shift grant data when checking correctness
|
2015-10-31 18:58:05 -07:00 |
|
Howard Mao
|
644b66a3a8
|
selectively enable or disable uncached and cached generators
|
2015-10-31 17:43:25 -07:00 |
|
Howard Mao
|
bcc631f756
|
generate word-size requests in uncached generator
|
2015-10-31 17:43:08 -07:00 |
|
Howard Mao
|
c1f42ce3d4
|
add an L1 cache request generator
|
2015-10-30 12:49:57 -07:00 |
|
Howard Mao
|
3103fa8da2
|
rename tl to mem in generator
|
2015-10-27 17:14:56 -07:00 |
|
Howard Mao
|
aeb9c86459
|
use the uncached port instead of the cached port
|
2015-10-26 23:09:36 -07:00 |
|
Howard Mao
|
b22088d934
|
make sure data checked is same as data sent
|
2015-10-26 21:55:04 -07:00 |
|
Howard Mao
|
2b252bc6ff
|
first commit
|
2015-10-26 21:43:50 -07:00 |
|