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Author SHA1 Message Date
Megan WachsandGitHub 7d146f3401 Merge pull request #1273 from freechipsproject/no_jtag_vpi 
Deprecate JTAGVPI
 2018-03-07 14:50:26 -08:00
Megan Wachs ef7a6115b7 vsim: don't need VPI without JTAGVPI 2018-03-07 10:58:09 -08:00
Megan Wachs 15dc7f6760 JTAGVPI: remove it from Chisel as it is unused 2018-03-07 10:55:45 -08:00
Megan Wachs 42e614550c JTAGVPI: remove it in favor of remote bitbang 2018-03-07 10:53:49 -08:00
Megan WachsandGitHub f1bd9c99aa Merge pull request #1262 from freechipsproject/beu-regfield 
Add BusErrorUnit RegFieldDesc
 2018-03-06 12:31:00 -08:00
Megan WachsandGitHub f00e9576e3 Merge pull request #1263 from freechipsproject/sim_jtag_reset 
SimJTAG: make the reset/init connectivity more flexible.
 2018-03-06 11:28:51 -08:00
Megan Wachs b669fb3d6a Merge remote-tracking branch 'origin/master' into beu-regfield 2018-03-06 11:04:17 -08:00
Megan WachsandGitHub 2a0e67ab15 Merge pull request #1267 from freechipsproject/plic_source_0 
PLIC: Update RegFieldDesc:  source 0 is different
 2018-03-06 11:03:26 -08:00
Megan Wachs a3d99e5ba2 DescribedReg: fix some imports 2018-03-06 11:02:10 -08:00
Megan Wachs a20998e215 SimJTAG: fix verilog typo 2018-03-05 16:27:17 -08:00
Megan Wachs 8856953905 DescribedReg: move to regmapper 2018-03-05 16:12:14 -08:00
Megan Wachs 4256d99a9b PLIC: priority/threshold are really WARL (RWSPECIAL). Explain why. 2018-03-05 16:10:05 -08:00
Megan Wachs 41d1a62713 PLIC: Update RegFieldDesc to reflect the fact that source 0 isn't like all the others 2018-03-05 15:29:14 -08:00
Megan Wachs bd3a72e585 Merge remote-tracking branch 'origin/master' into sim_jtag_reset 2018-03-05 12:41:39 -08:00
Megan Wachs e3be5db3e6 BUE: more verbose register descriptions 2018-03-05 12:02:42 -08:00
Megan Wachs 878a357a0d RegFieldDesc: Add utilities for generating and describing registers at the same time. 2018-03-05 12:02:42 -08:00
Megan Wachs 5eae81038d SimJTAG: make the reset/init connectivity more flexible. This is because you may want to seperate the two 2018-03-02 17:29:17 -08:00
Megan WachsandGitHub cdd2a9227f Merge pull request #1256 from freechipsproject/json_emit_enums 
RegFieldDesc: Emit enumerations into JSON if they exist
 2018-02-28 11:32:14 -08:00
Megan Wachs d13dc8ac2a RegFieldDesc: Emit enumerations if they exist 2018-02-28 09:42:25 -08:00
Megan WachsandGitHub db35f45bf7 Merge pull request #1242 from freechipsproject/unnamed_reg_fix 
RegFieldDesc: fix the output produced for undescribed registers
 2018-02-16 14:27:53 -08:00
Megan Wachs 5affd3bec2 RegFieldDesc: fix the output produced for undescribed registers 2018-02-16 10:24:12 -08:00
Megan WachsandGitHub cf7cd03d64 Merge pull request #1239 from freechipsproject/reduce_debug_flags 
Reduce Debug Module "flags"
 2018-02-16 08:53:41 -08:00
Megan WachsandGitHub d72abb7a12 Debug: revert change to how flags are named 2018-02-15 21:49:32 -08:00
Megan WachsandGitHub c34b940d9a ElaborationArtefacts: revert unintentional change 2018-02-15 14:23:54 -08:00
Megan WachsandGitHub e0c3b22d61 RegFieldDesc: same string used to insert/compare 2018-02-15 14:23:27 -08:00
Megan Wachs b95f68447f RegFieldDesc: Prevent different RegField JSONS from overwriting eachother. 2018-02-15 14:01:47 -08:00
Megan Wachs 64d3731e45 RegFieldDesc: don't put characters into names that need to be sanitized 2018-02-15 13:25:06 -08:00
Megan Wachs 197699b93a Debug: don't need to fully populate flags array 2018-02-15 13:23:51 -08:00
Megan WachsandGitHub e2e678d53d Merge pull request #1183 from freechipsproject/regfield_descriptions 
more detailed RegField descriptions
 2018-02-12 14:25:06 -08:00
Megan WachsandGitHub 6f70d25ef9 Merge pull request #1184 from freechipsproject/regfield_json 
TLRegMapper: emit a JSON file describing the register fields
 2018-02-12 12:00:01 -08:00
Megan Wachs de91672e9a RegFieldDesc: simplify the output RegFieldDesc JSON to just a list of reg fields 2018-02-12 08:32:52 -08:00
Megan Wachs 7bf0121f07 PLIC: correct some descriptions 2018-02-12 08:31:29 -08:00
Megan Wachs 08acbe1a29 RegFieldDesc: Clean up both descriptions and JSON presentations 2018-02-11 23:57:57 -08:00
Megan Wachs 5ab4204e8a RegField: the JSON will just leave things out of type None 2018-02-11 22:51:36 -08:00
Megan Wachs 3b44f380d8 TLRegMapper: emit a JSON file describing the register fields 2018-02-11 22:51:36 -08:00
Megan Wachs 256f8ffc6b Clint: Annotate regmap with RegFieldDesc 2018-02-11 21:33:09 -08:00
Megan Wachs 718c88a8f9 PLIC: Annotate regmap with RegFieldDescs 2018-02-11 21:05:17 -08:00
Megan Wachs 13b120fb01 Debug: Annotate regmaps with RegFieldDescs 2018-02-10 20:11:24 -08:00
Megan Wachs 7abf6e1c8a RegMapper: Update cover props to use new RegFieldDesc objects 2018-02-10 13:17:38 -08:00
Megan Wachs 4ab1585a78 Register Field: Add a more verbose description object 
Add versions of the RegField functions to take it in, and
update Example device to use it.
 2018-02-10 13:17:18 -08:00
Megan WachsandGitHub 338e453a91 JTAG: Use new withClock way of overriding clocks (#1072) 
* JTAG: Use new withClock way of overriding clocks

the override clock way is deprecated

* JTAG: use withClock instead of override clock

* JTAG:  extend Module for ClockedCounter

* JTAG: Don't use deprecated clock constructs

* JTAG: Remove another override_clock

* Rename "NegativeEdgeLatch"

because it's not a latch, it's just a register on the negative edge of the clock.

* Use the appropriately named NegEdgeReg

* JTAG: Rename another NegativeEdgeLatch
 2018-01-17 13:59:05 -08:00
Megan WachsandGitHub 6c6afc5bc9 Merge pull request #1191 from edcote/patch-2 
remove string type ambiguity in header
 2018-01-15 13:33:27 -08:00
Megan WachsandGitHub 8799508b1f Merge pull request #1179 from freechipsproject/refactored_rbb 
Add Debug tests to Regressions
 2018-01-12 10:34:48 -08:00
Megan Wachs 5fe0bb0d6a Merge remote-tracking branch 'origin/master' into refactored_rbb 2018-01-09 21:34:14 -08:00
Megan Wachs a530646d15 Merge remote-tracking branch 'origin/master' into refactored_rbb 2018-01-08 09:11:27 -08:00
Megan Wachs 427b6c9ab8 Emulator: Update it to allow some hard-coded Verilog PlusArgs 2018-01-05 17:08:21 -08:00
Megan Wachs 76c5fd0c0c travis: Use newer infrastructure, but require sudo for additional disk space. 
This is because as of Dec 12, 2017, Travis changed their container images and seem
to give slightly less disk space. Using a sudo image gives more disk space.
 2018-01-05 17:08:21 -08:00
Megan Wachs e6661a6982 Debug regressions: use a plusarg to enable remote bitbang. 2018-01-05 17:08:21 -08:00
Megan Wachs b643f3dca6 debug regressions: some whitespace and null ptr cleanup 2018-01-05 17:08:21 -08:00
Megan Wachs a97add954a Async Reg: Doesn't properly reset for Verilator. 2018-01-05 17:08:21 -08:00
Megan Wachs 9df3604007 emulator: No reason not to emit waveforms during reset 2018-01-05 17:08:21 -08:00
Megan Wachs 024cd52c44 debug: attempt to make the simulation deterministic by not returning until connection is made and command is receieved 2018-01-05 17:08:21 -08:00
Megan Wachs 1d3fa07c44 debug: print failures when debug tests fail, so we can see why it is failing on Travis 
Cleanups, and print out log names ASAP.

Factor out gdbserver common invocation into GDBSERVER (fixing
--print-failtures).
Add --print-log-names to that command so the logfiles can be inspected
while the simulation is still running.
`RISCV=... cmd` is more idiomatic than `export RISCV=... && cmd`
 2018-01-05 17:08:15 -08:00
Megan Wachs 9b234216f0 debug: Install pexpect package for travis regressions 2018-01-05 16:13:19 -08:00
Megan Wachs 1549ecfb3f debug: explicitly clone riscv-tests to get to gdbserver.py 2018-01-05 16:13:11 -08:00
Megan Wachs 3de9a04272 debug regression: until XLEN fix is merged into riscv-tests, have to explicitly state the XLEN 2018-01-05 16:10:13 -08:00
Megan Wachs bd5fe5d22e Debug regression: have to say something about memory in order to run a simple test 2018-01-05 16:10:13 -08:00
Megan Wachs 5df55d7911 debug regression: bump riscv-tools for riscv-tests fixes 2018-01-05 16:10:13 -08:00
Megan Wachs 593839e0d5 Debug: add Debug regression to Travis regressions. 2018-01-05 16:10:00 -08:00
Megan Wachs 4449dd0baa Debug regressions: Add necessary config scripts 2018-01-05 16:03:59 -08:00
Megan Wachs e82328336e Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. 
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
 2018-01-05 16:02:52 -08:00
Megan WachsandGitHub 74d9326ebc JTAG: Revert to Chisel._ for Issue 1160 (#1161) 
* JTAG: Revert to Chisel._ for Issue 1160

* JTAG: Revert to Chisel._ for Issue 1160

* jtag: revert everything to Chisel._

* jtag: Revert all modules to Chisel._ vs chisel3, due to FIRRTL issues with chisel3 generated code
 2017-12-18 21:02:31 -08:00
Megan WachsandGitHub 9d489c6dcd Merge pull request #1128 from freechipsproject/chisel_527_fixed 
debug: Remove workaround for Chisel 3 #527
 2017-11-27 16:53:02 -08:00
Megan Wachs f554ad7e2c debug: Remove workaround for Chisel 3 #527 2017-11-27 10:50:15 -08:00
Megan WachsandGitHub 6229c7b1ff Merge pull request #1117 from freechipsproject/debug_test_tools 
debug: bump riscv-tools/riscv-tests/debug for Priv test fixes
 2017-11-17 20:54:41 -08:00
Megan Wachs 68c5981363 debug: bump riscv-tools/riscv-tests/debug for Priv test fixes 2017-11-17 16:06:50 -08:00
Megan WachsandGitHub e7704f46c8 Add some add'l debug features (#1112) 
* debug: Update macros from spec

* debug: some corrections in the auto-generated files

* debug: update renamed fields

* Debug: implement the implicit ebreak option for small program buffers

* debug: clean up some unused code and add more require() explanations

* debug: make implicit ebreak false

* debug: Add the havereset/haveresetack functionality

* debug: program buffer can still be 16 even if there is an implicit ebreak
 2017-11-16 17:14:41 -08:00
Megan WachsandGitHub 7e75d63ba6 debug: Bump riscv-tools for riscv-tests timeout fix (#1086) 
* debug: Bump riscv-tools for riscv-tests timeout fix

* bump riscv-tools now that is merged into master
 2017-11-02 14:05:02 -07:00
Megan WachsandGitHub f86489b59e JTAG: Use sorted map for stability (#1073) 
* JTAG: Use sorted map for stability

Otherwise the generated FIRRTL/Verilog is non deterministic

* jtag : parens for clarity

* jtag: Use deterministic ListMap and sort for stability

* JTAG: use slightly clearer SortedMap (clearer to me anyway)

* jtag: whitespace cleanup
 2017-10-31 15:33:41 -07:00
Megan WachsandGitHub 897b686377 Merge pull request #1066 from freechipsproject/diplomacy_paper 
Add link to Diplomatic Design Patterns Paper
 2017-10-23 16:52:01 -07:00
Megan WachsandGitHub ffffafc7c3 Add link to Diplomatic Design Patterns Paper 2017-10-23 15:21:46 -07:00
Megan WachsandGitHub e9e05b5f3b Add a check that MaxHartIdBits is enough for all hartids (#1054) 
* Add a check that MaxHartIdBits is enough for all hartids

* Correct off-by-one error in hartid check
 2017-10-13 15:20:35 -07:00
Megan Wachs 7b4c48d005 Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars 2017-10-11 15:10:50 -07:00
Megan WachsandGitHub 0e6aa7ae9d Merge pull request #1024 from freechipsproject/jtag_coverage 
Add Coverage points for JTAG TAP
 2017-10-09 12:29:18 -07:00
Megan Wachs 0916cf1bdd JTAG Coverage: Correct jtag_reset case 2017-10-09 09:54:15 -07:00
Megan Wachs 9efe1c448e Merge remote-tracking branch 'origin/master' into HEAD 2017-10-09 09:48:38 -07:00
Megan Wachs 9c9cb68462 JTAG Coverage: Add reset coverage points 2017-10-02 11:08:13 -07:00
Megan Wachs a8ab06d572 JTAG: Add coverage points to the JTAG Tap 2017-10-02 11:08:13 -07:00
Megan WachsandGitHub ffa3ab29ac Merge pull request #1006 from freechipsproject/async_reset_reg 
async_reset_reg: Don't randomize the register if rst is asserted anyway
 2017-09-21 11:48:04 -07:00
Megan Wachs cda89fbacb async_reset_reg: Don't randomize the register if rst is asserted anyway 2017-09-20 14:47:00 -07:00
Megan WachsandGitHub cbd65cd247 Merge pull request #992 from freechipsproject/test_mode_reset 
reset_catch: Allow Test Mode Overrides
 2017-09-18 14:16:49 -07:00
Megan Wachs 826fc8ba61 Merge remote-tracking branch 'origin/master' into test_mode_reset 2017-09-18 09:50:27 -07:00
Megan Wachs c85333f826 Merge remote-tracking branch 'origin/test_mode_reset' into test_mode_reset 2017-09-17 13:51:46 -07:00
Megan Wachs 215e072e5c test_mode_reset: fix typos 2017-09-17 13:51:40 -07:00
Megan Wachs 641a8e7eab test_mode_reset: Correct some gender issues. Tie off signals in the test harness 2017-09-15 16:36:35 -07:00
Megan Wachs 6cda4504ac test_mode_reset: use a cleaner interface with bundles and options instead of individual signals 2017-09-15 12:30:39 -07:00
Megan Wachs ffc514d1bc test_mode_reset: Add missing file 2017-09-14 13:17:37 -07:00
Megan Wachs a0396b63e8 test_mode_reset: fix one bulk-connect gender issue 2017-09-14 13:16:13 -07:00
Megan Wachs 44edc5fdc3 test_mode_reset: Use simpler apply() method 2017-09-14 13:16:13 -07:00
Megan Wachs 82c00cb656 reset_catch: Allow Test Mode Overrides 2017-09-14 13:16:13 -07:00
Megan WachsandGitHub 929a924779 Merge pull request #975 from freechipsproject/async_reg 
Cleanup some register primitives
 2017-09-07 13:32:54 -07:00
Megan Wachs 1320f65ae6 Merge remote-tracking branch 'origin/master' into async_reg 2017-09-07 11:27:36 -07:00
Megan WachsandGitHub b7acb6ca3d Merge pull request #986 from freechipsproject/jtag_vpi_reset 
jtag_vpi: add some hysteresis for waiting for init_done
 2017-09-07 11:26:42 -07:00
Megan Wachs 126d56b254 synchronizers: I learn how foldRight works 2017-09-07 10:48:27 -07:00
Megan Wachs 1da6cb85ab shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created. 2017-09-07 09:57:50 -07:00
Megan WachsandGitHub f68390e458 jtag_vpi: Use a parameter for INIT_DELAY vs constant 2017-09-07 09:06:07 -07:00
Megan Wachs 19eabb6728 jtag_vpi: add some hysterisis for waiting for init_done 2017-09-06 18:13:04 -07:00
Megan Wachs dcafb5fea3 Merge remote-tracking branch 'origin/master' into async_reg 2017-09-06 11:07:19 -07:00
Megan Wachs 3c4b472f66 shift regs: remove some unnecessary primitives, and add some that actually are necessary 2017-09-06 10:37:59 -07:00
Megan Wachs 777f052f95 regs: Add named/initial value ShiftRegister primitives so they are all in one place 2017-09-05 17:32:53 -07:00