riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Debug regressions: use a plusarg to enable remote bitbang.

Browse Source
This commit is contained in:
Megan Wachs
2017-12-19 17:13:08 -08:00
parent b643f3dca6
commit e6661a6982
4 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
csrc/emulator.cc
View File

@ -220,9 +220,6 @@ done_processing:
jtag = new remote_bitbang_t(0);
dtm = new dtm_t(htif_argc, htif_argv);
jtag = new remote_bitbang_t(0);
dtm = new dtm_t(to_dtm);
signal(SIGTERM, handle_sigterm);
bool dump;

1
csrc/remote_bitbang.cc
View File

@ -69,6 +69,7 @@ remote_bitbang_t::remote_bitbang_t(uint16_t port) :
trstn = 1;
quit = 0;
printf ("This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.\n");
printf("Listening on port %d\n",
ntohs(addr.sin_port));
fflush(stdout);

10
regression/Makefile
View File

@ -231,6 +231,8 @@ ifdef SEED
SEED_ARG = --seed $(SEED)
endif
JTAG_DTM_SIM_ARGS = +verbose +jtag_rbb_enable=1 $(SEED_ARG)
stamps/riscv-tests.stamp:
git -C $(abspath $(TOP)) submodule update --init riscv-tools
git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-tests
@ -238,7 +240,7 @@ stamps/riscv-tests.stamp:
stamps/%/vsim-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp
RISCV=$(RISCV) $(GDBSERVER) \
--sim_cmd="$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(SEED_ARG) $(VSIM_JTAG_VCDPLUS_32)" \
--sim_cmd="$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) $(JTAG_DTM_SIM_ARGS) $(VSIM_JTAG_VCDPLUS_32)" \
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
-s $(RISCV)/share/openocd/scripts" \
--32 \
@ -248,7 +250,7 @@ stamps/%/vsim-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
stamps/%/vsim-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp
RISCV=$(RISCV) $(GDBSERVER) \
--sim_cmd="$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(SEED_ARG) $(VSIM_JTAG_VCDPLUS_64)" \
--sim_cmd="$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) $(JTAG_DTM_SIM_ARGS) $(VSIM_JTAG_VCDPLUS_64)" \
--server_cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd $(OPENOCD_DEBUG) \
-s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
--64 \
@ -258,7 +260,7 @@ stamps/%/vsim-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
stamps/%/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp
RISCV=$(RISCV) $(GDBSERVER) \
--sim_cmd="$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(SEED_ARG) $(EMULATOR_JTAG_VCDPLUS_32) dummybin" \
--sim_cmd="$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) $(JTAG_DTM_SIM_ARGS) $(EMULATOR_JTAG_VCDPLUS_32) dummybin" \
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
-s $(RISCV)/share/openocd/scripts" \
--32 \
@ -268,7 +270,7 @@ stamps/%/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_S
stamps/%/emulator-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp
RISCV=$(RISCV) $(GDBSERVER) \
--sim_cmd="$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(SEED_ARG) $(EMULATOR_JTAG_VCDPLUS_64) dummybin" \
--sim_cmd="$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) $(JTAG_DTM_SIM_ARGS) $(EMULATOR_JTAG_VCDPLUS_64) dummybin" \
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
-s $(RISCV)/share/openocd/scripts" \
--64 \

2
src/main/scala/devices/debug/Periphery.scala
View File

@ -130,7 +130,7 @@ class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam
io.clock := tbclock
io.reset := tbreset
io.enable := ~tbreset
io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
io.init_done := ~tbreset
// Success is determined by the gdbserver