riscv/rocket-chip
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test_mode_reset: Correct some gender issues. Tie off signals in the test harness

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This commit is contained in:
Megan Wachs 2017-09-15 16:36:35 -07:00
parent 6cda4504ac
commit 641a8e7eab
3 changed files with 12 additions and 8 deletions
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4
src/main/scala/devices/debug/Debug.scala
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@ -1067,7 +1067,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
val dmi = new ClockedDMIIO().flip
val in = node.bundleIn
val debugInterrupts = intnode.bundleOut
val psd = new PSDTestMode()
val psd = new PSDTestMode().asInput
}
dmOuter.module.io.dmi <> io.dmi.dmi
@ -1078,7 +1078,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive
dmInner.module.io.debugUnavail := io.ctrl.debugUnavail
io.psd <> dmInner.module.io.psd
dmInner.module.io.psd <> io.psd
io.ctrl <> dmOuter.module.io.ctrl

14
src/main/scala/devices/debug/Periphery.scala
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@ -38,7 +38,7 @@ trait HasPeripheryDebugBundle {
val debug: DebugIO
def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2) {
def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2, psd: PSDTestMode) {
debug.clockeddmi.foreach { d =>
val dtm = Module(new SimDTM).connect(c, r, d, out)
}
@ -46,7 +46,12 @@ trait HasPeripheryDebugBundle {
val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
}
debug.psd.foreach { _ <> psd }
}
def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2) =
connectDebug(c, r, out, tckHalfPeriod, cmdDelay, new PSDTestMode.fromBits(0.U))
}
trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle {
val outer: HasPeripheryDebug
@ -57,8 +62,6 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD
val dtm = debug.systemjtag.map { sj =>
val psd = debug.psd.getOrElse(Wire(init = new PSDTestMode().fromBits(0.U)))
val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleParams).nDMIAddrSize, p(JtagDTMKey)))
dtm.io.jtag <> sj.jtag
@ -70,8 +73,9 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD
outer.debug.module.io.dmi.dmi <> dtm.io.dmi
outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK
psd <> outer.debug.module.io.psd
outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd)
val psd = debug.psd.getOrElse(Wire(new PSDTestMode).fromBits(0.U))
outer.debug.module.io.psd <> psd
outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd)
dtm
}

2
src/main/scala/util/ResetCatchAndSync.scala
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@ -26,7 +26,7 @@ class ResetCatchAndSync (sync: Int = 3) extends Module {
object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
psd: Option[PSDTestMode] =None): Bool = {
psd: Option[PSDTestMode] = None): Bool = {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}