RegFieldDesc: fix the output produced for undescribed registers
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@ -88,7 +88,7 @@ case class TLRegisterNode(
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val regDescs = mapping.flatMap { case (offset, seq) =>
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var currentBitOffset = 0
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seq.zipWithIndex.map { case (f, i) => {
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val tmp = (f.desc.map{ _.name}.getOrElse(s"unnamedRegField${i}") -> (
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val tmp = (f.desc.map{ _.name}.getOrElse(s"unnamedRegField${offset.toHexString}_${currentBitOffset}") -> (
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("byteOffset" -> s"0x${offset.toHexString}") ~
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("bitOffset" -> currentBitOffset) ~
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("bitWidth" -> f.width) ~
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