Merge pull request #1184 from freechipsproject/regfield_json
TLRegMapper: emit a JSON file describing the register fields
This commit is contained in:
Megan Wachs
GitHub
commit
6f70d25ef9
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@ -15,6 +15,7 @@ lazy val commonSettings = Seq(
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traceLevel := 15,
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scalacOptions ++= Seq("-deprecation","-unchecked"),
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libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value),
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libraryDependencies ++= Seq("org.json4s" %% "json4s-jackson" % "3.5.0"),
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addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full)
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)
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@ -44,3 +45,4 @@ val chipSettings = Seq(
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s"make -C $makeDir -j $jobs $target".!
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}
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)
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@ -83,9 +83,9 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
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*/
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node.regmap(
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0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.map{ case (r, i) => RegField(ipiWidth, r, RegFieldDesc(s"msip_$i", "MSIP bit for Hart $i", reset=Some(0)))}),
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0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.map{ case (r, i) => RegField(ipiWidth, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0)))}),
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timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) =>
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RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc("mtimecmp_$i", "", reset=None))))},
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RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))},
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timeOffset -> RegFieldGroup("mtime", Some("Timer Register"), RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0)))))
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)
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}
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@ -179,8 +179,8 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
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PLICConsts.enableBase(i) -> RegFieldGroup("enable", Some("Enable bits for each interrupt source. 1 bit for each interrupt source."),
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e.map(b => RegField(1, b, RegFieldDesc(s"enable_$i", "Enable interrupt and claim for source $i", reset=None))))
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PLICConsts.enableBase(i) -> RegFieldGroup(s"enables_${i}", Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source."),
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e.zipWithIndex.map{case (b, j) => RegField(1, b, RegFieldDesc(s"enable_${i}_${j}", s"Enable interrupt for source $j for target $i.", reset=None))})
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}
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// When a hart reads a claim/complete register, then the
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@ -232,8 +232,9 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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completer(i) := valid && enables(i)(completerDev)
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Bool(true)
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},
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Some(RegFieldDesc(s"claim_complete_$i", ("Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." +
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"Writing the interrupt number back completes the interrupt."),
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Some(RegFieldDesc(s"claim_complete_$i",
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s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." +
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s"Writing the interrupt number back completes the interrupt.",
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reset = None,
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access = RegFieldAccessType.RWSPECIAL))
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)
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@ -164,7 +164,7 @@ object RegField
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val valids = Wire(init = Vec.fill(numBytes) { Bool(false) })
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when (valids.reduce(_ || _)) { reg := newBytes.asUInt }
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Seq.tabulate(numBytes) { i =>
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val newDesc = desc.map {d => d.copy(name = d.name + s"[${i*8-1}:${i*8}]")}
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val newDesc = desc.map {d => d.copy(name = d.name + s"[${(i+1)*8-1}:${i*8}]")}
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RegField(8, oldBytes(i),
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RegWriteFn((valid, data) => {
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valids(i) := valid
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@ -7,9 +7,12 @@ import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util.HeterogeneousBag
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import freechips.rocketchip.util.{HeterogeneousBag, ElaborationArtefacts}
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import scala.math.{min,max}
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import org.json4s.JsonDSL._
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import org.json4s.jackson.JsonMethods.{pretty, render}
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case class TLRegisterNode(
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address: Seq[AddressSet],
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device: Device,
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@ -80,6 +83,35 @@ case class TLRegisterNode(
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bundleIn.b.valid := Bool(false)
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bundleIn.c.ready := Bool(true)
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bundleIn.e.ready := Bool(true)
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// Dump out the register map for documentation purposes.
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val regDescs = mapping.flatMap { case (offset, seq) =>
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var currentBitOffset = 0
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seq.zipWithIndex.map { case (f, i) => {
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val tmp = (f.desc.map{ _.name}.getOrElse(s"unnamedRegField${i}") -> (
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("byteOffset" -> s"0x${offset.toHexString}") ~
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("bitOffset" -> currentBitOffset) ~
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("bitWidth" -> f.width) ~
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("name" -> f.desc.map(_.name)) ~
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("description" -> f.desc.map{ d=> if (d.desc == "") None else Some(d.desc)}) ~
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("resetValue" -> f.desc.map{_.reset}) ~
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("group" -> f.desc.map{_.group}) ~
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("groupDesc" -> f.desc.map{_.groupDesc}) ~
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("accessType" -> f.desc.map {d => d.access.toString})
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))
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currentBitOffset = currentBitOffset + f.width
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tmp
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}}
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}
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//TODO: It would be better to name this other than "Device at ...."
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val base = s"0x${address.head.base.toInt.toHexString}"
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val json = ("peripheral" -> (
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("displayName" -> s"deviceAt${base}") ~
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("baseAddress" -> base) ~
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("regfields" -> regDescs)
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))
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ElaborationArtefacts.add(s"${base}.regmap.json", pretty(render(json)))
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}
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}
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