Merge pull request #1179 from freechipsproject/refactored_rbb
Add Debug tests to Regressions
This commit is contained in:
Megan Wachs
GitHub
commit
8799508b1f
11
.travis.yml
11
.travis.yml
@ -1,8 +1,7 @@
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git:
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submodules: false
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language: scala
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# run on new infrastructure
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sudo: false
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sudo: required
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cache:
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apt: true
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directories:
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@ -32,6 +31,7 @@ addons:
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- texinfo
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- device-tree-compiler
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- libusb-1.0-0-dev
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- python-pexpect
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# blacklist private branches
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@ -69,6 +69,11 @@ jobs:
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- export CXX=g++-4.8 CC=gcc-4.8
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- &test
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stage: Test
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script:
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- travis_wait 80 make emulator-ndebug -C regression SUITE=JtagDtmSuite JVM_MEMORY=3G
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- travis_wait 80 make emulator-jtag-dtm-tests-32 -C regression SUITE=JtagDtmSuite JVM_MEMORY=3G
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- travis_wait 80 make emulator-jtag-dtm-tests-64 -C regression SUITE=JtagDtmSuite JVM_MEMORY=3G
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- <<: *test
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script:
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- travis_wait 80 make emulator-ndebug -C regression SUITE=UnittestSuite JVM_MEMORY=3G
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- travis_wait 80 make emulator-regression-tests -C regression SUITE=UnittestSuite JVM_MEMORY=3G
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@ -83,4 +88,4 @@ jobs:
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- <<: *test
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script:
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- travis_wait 80 make emulator-ndebug -C regression SUITE=RocketSuiteA JVM_MEMORY=3G
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- travis_wait 80 make emulator-regression-tests -C regression SUITE=RocketSuiteA JVM_MEMORY=3G
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- travis_wait 80 make emulator-regression-tests -C regression SUITE=RocketSuiteA JVM_MEMORY=3G
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@ -6,27 +6,6 @@
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dtm_t* dtm;
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namespace {
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// Remove args that will confuse dtm, such as those that require two tokens, like VCS code coverage "-cm line+cond"
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std::vector<std::string> filter_argv_for_dtm(int argc, char** argv)
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{
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std::vector<std::string> out;
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for (int i = 1; i < argc; ++i) { // start with 1 to skip my executable name
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if (!strncmp(argv[i], "-cm", 3)) {
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++i; // skip this one and the next one
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}
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else {
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out.push_back(argv[i]);
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}
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}
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return out;
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}
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}
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extern "C" int debug_tick
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(
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unsigned char* debug_req_valid,
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@ -44,7 +23,7 @@ extern "C" int debug_tick
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s_vpi_vlog_info info;
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if (!vpi_get_vlog_info(&info))
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abort();
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dtm = new dtm_t(filter_argv_for_dtm(info.argc, info.argv));
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dtm = new dtm_t(info.argc, info.argv);
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}
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dtm_t::resp resp_bits;
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32
csrc/SimJTAG.cc
Normal file
32
csrc/SimJTAG.cc
Normal file
@ -0,0 +1,32 @@
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// See LICENSE.SiFive for license details.
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#include <vpi_user.h>
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#include <svdpi.h>
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#include <cstdlib>
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#include "remote_bitbang.h"
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remote_bitbang_t* jtag;
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extern "C" int jtag_tick
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(
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unsigned char * jtag_TCK,
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unsigned char * jtag_TMS,
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unsigned char * jtag_TDI,
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unsigned char * jtag_TRSTn,
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unsigned char jtag_TDO
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)
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{
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if (!jtag) {
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s_vpi_vlog_info info;
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if (!vpi_get_vlog_info(&info)) {
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abort();
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}
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// TODO: Pass in real port number
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jtag = new remote_bitbang_t(0);
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}
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jtag->tick(jtag_TCK, jtag_TMS, jtag_TDI, jtag_TRSTn, jtag_TDO);
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return jtag->done() ? (jtag->exit_code() << 1 | 1) : 0;
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}
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194
csrc/emulator.cc
194
csrc/emulator.cc
@ -6,6 +6,7 @@
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#include "verilated_vcd_c.h"
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#endif
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#include <fesvr/dtm.h>
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#include "remote_bitbang.h"
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#include <iostream>
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#include <fcntl.h>
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#include <signal.h>
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@ -14,7 +15,16 @@
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#include <unistd.h>
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#include <getopt.h>
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//TODO: GENERATE THESE AUTOMATICALLY!
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static const char * verilog_plusargs [] = { "max-core-cycles",
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"jtag_rbb_enable",
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"tilelink_timeout",
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0};
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extern dtm_t* dtm;
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extern remote_bitbang_t * jtag;
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static uint64_t trace_count = 0;
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bool verbose;
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bool done_reset;
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@ -34,33 +44,58 @@ extern "C" int vpi_get_vlog_info(void* arg)
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return 0;
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}
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static void usage(const char * program_name) {
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printf("Usage: %s [OPTION]... BINARY [BINARY ARGS]\n", program_name);
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static void usage(const char * program_name)
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{
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printf("Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]...\n",
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program_name);
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fputs("\
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Run a BINARY on the Rocket Chip emulator.\n\
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\n\
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Mandatory arguments to long options are mandatory for short options too.\n\
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-c, --cycle-count print the cycle count before exiting\n\
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\n\
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EMULATOR OPTIONS\n\
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-c, --cycle-count Print the cycle count before exiting\n\
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+cycle-count\n\
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-h, --help display this help and exit\n\
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-m, --max-cycles=CYCLES kill the emulation after CYCLES\n\
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-h, --help Display this help and exit\n\
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-m, --max-cycles=CYCLES Kill the emulation after CYCLES\n\
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+max-cycles=CYCLES\n\
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-s, --seed=SEED use random number seed SEED\n\
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-V, --verbose enable all Chisel printfs\n\
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-s, --seed=SEED Use random number seed SEED\n\
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-V, --verbose Enable all Chisel printfs (cycle-by-cycle info)\n\
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+verbose\n\
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", stdout);
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#if VM_TRACE
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#if VM_TRACE == 0
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fputs("\
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-v, --vcd=FILE, write vcd trace to FILE (or '-' for stdout)\n\
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-x, --dump-start=CYCLE start VCD tracing at CYCLE\n\
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+dump-start\n\
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", stdout);
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#else
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fputs("\
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VCD options (e.g., -v, +dump-start) require a debug-enabled emulator.\n\
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Try `make debug`.\n\
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", stdout);
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\n\
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EMULATOR OPTIONS (only supported in debug build -- try `make debug`)\n",
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stdout);
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#endif
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fputs("\
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-v, --vcd=FILE, Write vcd trace to FILE (or '-' for stdout)\n\
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-x, --dump-start=CYCLE Start VCD tracing at CYCLE\n\
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+dump-start\n\
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", stdout);
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fputs("\
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\n\
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VERILOG PLUSARGS (accepted by the Verilog itself):\n" , stdout);
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const char ** vpa = &verilog_plusargs[0];
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while (*vpa) {
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fprintf(stdout, " +%s=...\n", *vpa);
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vpa ++;
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}
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fputs("\n" HTIF_USAGE_OPTIONS, stdout);
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printf("\n"
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"EXAMPLES\n"
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" - run a bare metal test:\n"
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" %s $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add\n"
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" - run a bare metal test showing cycle-by-cycle information:\n"
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" %s +verbose $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add 2>&1 | spike-dasm\n"
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#if VM_TRACE
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" - run a bare metal test to generate a VCD waveform:\n"
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" %s -v rv64ui-p-add.vcd $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add\n"
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#endif
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" - run an ELF (you wrote, called 'hello') using the proxy kernel:\n"
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" %s pk hello\n",
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program_name, program_name, program_name, program_name);
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}
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int main(int argc, char** argv)
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@ -73,8 +108,9 @@ int main(int argc, char** argv)
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FILE * vcdfile = NULL;
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uint64_t start = 0;
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#endif
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std::vector<std::string> to_dtm;
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char ** htif_argv = NULL;
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int verilog_plusargs_legal = 1;
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while (1) {
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static struct option long_options[] = {
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{"cycle-count", no_argument, 0, 'c' },
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@ -86,7 +122,7 @@ int main(int argc, char** argv)
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{"vcd", required_argument, 0, 'v' },
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{"dump-start", required_argument, 0, 'x' },
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#endif
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{0, 0, 0, 0}
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HTIF_LONG_OPTIONS
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};
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int option_index = 0;
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#if VM_TRACE
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@ -95,8 +131,9 @@ int main(int argc, char** argv)
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int c = getopt_long(argc, argv, "-chm:s:V", long_options, &option_index);
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#endif
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if (c == -1) break;
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retry:
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switch (c) {
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// Process "normal" options with '--' long options or '-' short options
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// Process long and short EMULATOR options
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case '?': usage(argv[0]); return 1;
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case 'c': print_cycles = true; break;
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case 'h': usage(argv[0]); return 0;
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@ -114,39 +151,86 @@ int main(int argc, char** argv)
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}
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case 'x': start = atoll(optarg); break;
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#endif
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// Processing of legacy '+' options and recognition of when
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// we've hit the binary. The binary is expected to be a
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// non-option and not start with '-' or '+'.
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// Process legacy '+' EMULATOR arguments by replacing them with
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// their getopt equivalents
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case 1: {
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std::string arg = optarg;
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if (arg == "+verbose")
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verbose = true;
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else if (arg.substr(0, 12) == "+max-cycles=")
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max_cycles = atoll(optarg+12);
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#if VM_TRACE
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else if (arg.substr(0, 12) == "+dump-start=")
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start = atoll(optarg+12);
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#endif
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else if (arg.substr(0, 12) == "+cycle-count")
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print_cycles = true;
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else {
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to_dtm.push_back(optarg);
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if (arg.substr(0, 1) != "+") {
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optind--;
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goto done_processing;
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}
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break;
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if (arg == "+verbose")
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c = 'V';
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else if (arg.substr(0, 12) == "+max-cycles=") {
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c = 'm';
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optarg = optarg+12;
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}
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#if VM_TRACE
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else if (arg.substr(0, 12) == "+dump-start=") {
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c = 'x';
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optarg = optarg+12;
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}
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#endif
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else if (arg.substr(0, 12) == "+cycle-count")
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c = 'c';
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// If we don't find a legacy '+' EMULATOR argument, it still could be
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// a VERILOG_PLUSARG and not an error.
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else if (verilog_plusargs_legal) {
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const char ** plusarg = &verilog_plusargs[0];
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int legal_verilog_plusarg = 0;
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while (*plusarg && (legal_verilog_plusarg == 0)){
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if (arg.substr(1, strlen(*plusarg)) == *plusarg) {
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legal_verilog_plusarg = 1;
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}
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plusarg ++;
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}
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if (!legal_verilog_plusarg) {
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verilog_plusargs_legal = 0;
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} else {
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c = 'P';
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}
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goto retry;
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}
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// If we STILL don't find a legacy '+' argument, it still could be
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// an HTIF (HOST) argument and not an error. If this is the case, then
|
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// we're done processing EMULATOR and VERILOG arguments.
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else {
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static struct option htif_long_options [] = { HTIF_LONG_OPTIONS };
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struct option * htif_option = &htif_long_options[0];
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while (htif_option->name) {
|
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if (arg.substr(1, strlen(htif_option->name)) == htif_option->name) {
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optind--;
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goto done_processing;
|
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}
|
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htif_option++;
|
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}
|
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std::cerr << argv[0] << ": invalid HTIF legacy plus-arg \"" << arg << "\"\n";
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c = '?';
|
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}
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goto retry;
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}
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case 'P': break; // Nothing to do here, Verilog PlusArg
|
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// Realize that we've hit HTIF (HOST) arguments or error out
|
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default:
|
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if (c >= HTIF_LONG_OPTIONS_OPTIND) {
|
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optind--;
|
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goto done_processing;
|
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}
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c = '?';
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goto retry;
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}
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}
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|
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done_processing:
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if (optind < argc)
|
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while (optind < argc)
|
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to_dtm.push_back(argv[optind++]);
|
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if (!to_dtm.size()) {
|
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if (optind == argc) {
|
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std::cerr << "No binary specified for emulator\n";
|
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usage(argv[0]);
|
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return 1;
|
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}
|
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int htif_argc = 1 + argc - optind;
|
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htif_argv = (char **) malloc((htif_argc) * sizeof (char *));
|
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htif_argv[0] = argv[0];
|
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for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++];
|
||||
|
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if (verbose)
|
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fprintf(stderr, "using random seed %u\n", random_seed);
|
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@ -168,26 +252,39 @@ done_processing:
|
||||
}
|
||||
#endif
|
||||
|
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dtm = new dtm_t(to_dtm);
|
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jtag = new remote_bitbang_t(0);
|
||||
dtm = new dtm_t(htif_argc, htif_argv);
|
||||
|
||||
signal(SIGTERM, handle_sigterm);
|
||||
|
||||
bool dump;
|
||||
// reset for several cycles to handle pipelined reset
|
||||
for (int i = 0; i < 10; i++) {
|
||||
tile->reset = 1;
|
||||
tile->clock = 0;
|
||||
tile->eval();
|
||||
#if VM_TRACE
|
||||
dump = tfp && trace_count >= start;
|
||||
if (dump)
|
||||
tfp->dump(static_cast<vluint64_t>(trace_count * 2));
|
||||
#endif
|
||||
tile->clock = 1;
|
||||
tile->eval();
|
||||
tile->reset = 0;
|
||||
#if VM_TRACE
|
||||
if (dump)
|
||||
tfp->dump(static_cast<vluint64_t>(trace_count * 2 + 1));
|
||||
#endif
|
||||
trace_count ++;
|
||||
}
|
||||
tile->reset = 0;
|
||||
done_reset = true;
|
||||
|
||||
while (!dtm->done() && !tile->io_success && trace_count < max_cycles) {
|
||||
while (!dtm->done() && !jtag->done() &&
|
||||
!tile->io_success && trace_count < max_cycles) {
|
||||
tile->clock = 0;
|
||||
tile->eval();
|
||||
#if VM_TRACE
|
||||
bool dump = tfp && trace_count >= start;
|
||||
dump = tfp && trace_count >= start;
|
||||
if (dump)
|
||||
tfp->dump(static_cast<vluint64_t>(trace_count * 2));
|
||||
#endif
|
||||
@ -213,6 +310,11 @@ done_processing:
|
||||
fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", dtm->exit_code(), random_seed, trace_count);
|
||||
ret = dtm->exit_code();
|
||||
}
|
||||
else if (jtag->exit_code())
|
||||
{
|
||||
fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", jtag->exit_code(), random_seed, trace_count);
|
||||
ret = jtag->exit_code();
|
||||
}
|
||||
else if (trace_count == max_cycles)
|
||||
{
|
||||
fprintf(stderr, "*** FAILED *** (timeout, seed %d) after %ld cycles\n", random_seed, trace_count);
|
||||
@ -224,6 +326,8 @@ done_processing:
|
||||
}
|
||||
|
||||
if (dtm) delete dtm;
|
||||
if (jtag) delete jtag;
|
||||
if (tile) delete tile;
|
||||
if (htif_argv) free(htif_argv);
|
||||
return ret;
|
||||
}
|
||||
|
||||
202
csrc/remote_bitbang.cc
Normal file
202
csrc/remote_bitbang.cc
Normal file
@ -0,0 +1,202 @@
|
||||
// See LICENSE.Berkeley for license details.
|
||||
|
||||
#include <arpa/inet.h>
|
||||
#include <errno.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <cstdio>
|
||||
#include <cstdlib>
|
||||
|
||||
#include "remote_bitbang.h"
|
||||
|
||||
/////////// remote_bitbang_t
|
||||
|
||||
remote_bitbang_t::remote_bitbang_t(uint16_t port) :
|
||||
socket_fd(0),
|
||||
client_fd(0),
|
||||
recv_start(0),
|
||||
recv_end(0)
|
||||
{
|
||||
socket_fd = socket(AF_INET, SOCK_STREAM, 0);
|
||||
if (socket_fd == -1) {
|
||||
fprintf(stderr, "remote_bitbang failed to make socket: %s (%d)\n",
|
||||
strerror(errno), errno);
|
||||
abort();
|
||||
}
|
||||
|
||||
fcntl(socket_fd, F_SETFL, O_NONBLOCK);
|
||||
int reuseaddr = 1;
|
||||
if (setsockopt(socket_fd, SOL_SOCKET, SO_REUSEADDR, &reuseaddr,
|
||||
sizeof(int)) == -1) {
|
||||
fprintf(stderr, "remote_bitbang failed setsockopt: %s (%d)\n",
|
||||
strerror(errno), errno);
|
||||
abort();
|
||||
}
|
||||
|
||||
struct sockaddr_in addr;
|
||||
memset(&addr, 0, sizeof(addr));
|
||||
addr.sin_family = AF_INET;
|
||||
addr.sin_addr.s_addr = INADDR_ANY;
|
||||
addr.sin_port = htons(port);
|
||||
|
||||
if (bind(socket_fd, (struct sockaddr *) &addr, sizeof(addr)) == -1) {
|
||||
fprintf(stderr, "remote_bitbang failed to bind socket: %s (%d)\n",
|
||||
strerror(errno), errno);
|
||||
abort();
|
||||
}
|
||||
|
||||
if (listen(socket_fd, 1) == -1) {
|
||||
fprintf(stderr, "remote_bitbang failed to listen on socket: %s (%d)\n",
|
||||
strerror(errno), errno);
|
||||
abort();
|
||||
}
|
||||
|
||||
socklen_t addrlen = sizeof(addr);
|
||||
if (getsockname(socket_fd, (struct sockaddr *) &addr, &addrlen) == -1) {
|
||||
fprintf(stderr, "remote_bitbang getsockname failed: %s (%d)\n",
|
||||
strerror(errno), errno);
|
||||
abort();
|
||||
}
|
||||
|
||||
tck = 1;
|
||||
tms = 1;
|
||||
tdi = 1;
|
||||
trstn = 1;
|
||||
quit = 0;
|
||||
|
||||
printf ("This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.\n");
|
||||
printf("Listening on port %d\n",
|
||||
ntohs(addr.sin_port));
|
||||
fflush(stdout);
|
||||
}
|
||||
|
||||
void remote_bitbang_t::accept()
|
||||
{
|
||||
|
||||
fprintf(stderr,"Attempting to accept client socket\n");
|
||||
int again = 1;
|
||||
while (again != 0) {
|
||||
client_fd = ::accept(socket_fd, NULL, NULL);
|
||||
if (client_fd == -1) {
|
||||
if (errno == EAGAIN) {
|
||||
// No client waiting to connect right now.
|
||||
} else {
|
||||
fprintf(stderr, "failed to accept on socket: %s (%d)\n", strerror(errno),
|
||||
errno);
|
||||
again = 0;
|
||||
abort();
|
||||
}
|
||||
} else {
|
||||
fcntl(client_fd, F_SETFL, O_NONBLOCK);
|
||||
fprintf(stderr, "Accepted successfully.");
|
||||
again = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void remote_bitbang_t::tick(
|
||||
unsigned char * jtag_tck,
|
||||
unsigned char * jtag_tms,
|
||||
unsigned char * jtag_tdi,
|
||||
unsigned char * jtag_trstn,
|
||||
unsigned char jtag_tdo
|
||||
)
|
||||
{
|
||||
if (client_fd > 0) {
|
||||
tdo = jtag_tdo;
|
||||
execute_command();
|
||||
} else {
|
||||
this->accept();
|
||||
}
|
||||
|
||||
* jtag_tck = tck;
|
||||
* jtag_tms = tms;
|
||||
* jtag_tdi = tdi;
|
||||
* jtag_trstn = trstn;
|
||||
|
||||
}
|
||||
|
||||
void remote_bitbang_t::reset(){
|
||||
//trstn = 0;
|
||||
}
|
||||
|
||||
void remote_bitbang_t::set_pins(char _tck, char _tms, char _tdi){
|
||||
tck = _tck;
|
||||
tms = _tms;
|
||||
tdi = _tdi;
|
||||
}
|
||||
|
||||
void remote_bitbang_t::execute_command()
|
||||
{
|
||||
char command;
|
||||
int again = 1;
|
||||
while (again) {
|
||||
ssize_t num_read = read(client_fd, &command, sizeof(command));
|
||||
if (num_read == -1) {
|
||||
if (errno == EAGAIN) {
|
||||
// We'll try again the next call.
|
||||
fprintf(stderr, "Received no command. Will try again on the next call\n");
|
||||
} else {
|
||||
fprintf(stderr, "remote_bitbang failed to read on socket: %s (%d)\n",
|
||||
strerror(errno), errno);
|
||||
again = 0;
|
||||
abort();
|
||||
}
|
||||
} else if (num_read == 0) {
|
||||
fprintf(stderr, "No Command Received.\n");
|
||||
again = 1;
|
||||
} else {
|
||||
again = 0;
|
||||
}
|
||||
}
|
||||
|
||||
fprintf(stderr, "Received a command %c\n", command);
|
||||
|
||||
int dosend = 0;
|
||||
|
||||
char tosend = '?';
|
||||
|
||||
switch (command) {
|
||||
case 'B': /* fprintf(stderr, "*BLINK*\n"); */ break;
|
||||
case 'b': /* fprintf(stderr, "_______\n"); */ break;
|
||||
case 'r': reset(); break; // This is wrong. 'r' has other bits that indicated TRST and SRST.
|
||||
case '0': set_pins(0, 0, 0); break;
|
||||
case '1': set_pins(0, 0, 1); break;
|
||||
case '2': set_pins(0, 1, 0); break;
|
||||
case '3': set_pins(0, 1, 1); break;
|
||||
case '4': set_pins(1, 0, 0); break;
|
||||
case '5': set_pins(1, 0, 1); break;
|
||||
case '6': set_pins(1, 1, 0); break;
|
||||
case '7': set_pins(1, 1, 1); break;
|
||||
case 'R': dosend = 1; tosend = tdo ? '1' : '0'; break;
|
||||
case 'Q': quit = 1; break;
|
||||
default:
|
||||
fprintf(stderr, "remote_bitbang got unsupported command '%c'\n",
|
||||
command);
|
||||
}
|
||||
|
||||
if (dosend){
|
||||
while (1) {
|
||||
ssize_t bytes = write(client_fd, &tosend, sizeof(tosend));
|
||||
if (bytes == -1) {
|
||||
fprintf(stderr, "failed to write to socket: %s (%d)\n", strerror(errno), errno);
|
||||
abort();
|
||||
}
|
||||
if (bytes > 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (quit) {
|
||||
// The remote disconnected.
|
||||
fprintf(stderr, "Remote end disconnected\n");
|
||||
close(client_fd);
|
||||
client_fd = 0;
|
||||
}
|
||||
}
|
||||
59
csrc/remote_bitbang.h
Normal file
59
csrc/remote_bitbang.h
Normal file
@ -0,0 +1,59 @@
|
||||
// See LICENSE.Berkeley for license details.
|
||||
|
||||
#ifndef REMOTE_BITBANG_H
|
||||
#define REMOTE_BITBANG_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
class remote_bitbang_t
|
||||
{
|
||||
public:
|
||||
// Create a new server, listening for connections from localhost on the given
|
||||
// port.
|
||||
remote_bitbang_t(uint16_t port);
|
||||
|
||||
// Do a bit of work.
|
||||
void tick(unsigned char * jtag_tck,
|
||||
unsigned char * jtag_tms,
|
||||
unsigned char * jtag_tdi,
|
||||
unsigned char * jtag_trstn,
|
||||
unsigned char jtag_tdo);
|
||||
|
||||
unsigned char done() {return quit;}
|
||||
|
||||
int exit_code() {return err;}
|
||||
|
||||
private:
|
||||
|
||||
int err;
|
||||
|
||||
unsigned char tck;
|
||||
unsigned char tms;
|
||||
unsigned char tdi;
|
||||
unsigned char trstn;
|
||||
unsigned char tdo;
|
||||
unsigned char quit;
|
||||
|
||||
int socket_fd;
|
||||
int client_fd;
|
||||
|
||||
static const ssize_t buf_size = 64 * 1024;
|
||||
char recv_buf[buf_size];
|
||||
ssize_t recv_start, recv_end;
|
||||
|
||||
// Check for a client connecting, and accept if there is one.
|
||||
void accept();
|
||||
// Execute any commands the client has for us.
|
||||
// But we only execute 1 because we need time for the
|
||||
// simulation to run.
|
||||
void execute_command();
|
||||
|
||||
// Reset. Currently does nothing.
|
||||
void reset();
|
||||
|
||||
void set_pins(char _tck, char _tms, char _tdi);
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
@ -8,7 +8,7 @@ output_dir = $(sim_dir)/output
|
||||
|
||||
include $(base_dir)/Makefrag
|
||||
|
||||
CXXSRCS := emulator SimDTM
|
||||
CXXSRCS := emulator SimDTM SimJTAG remote_bitbang
|
||||
CXXFLAGS := $(CXXFLAGS) -std=c++11 -I$(RISCV)/include -I$(base_dir)/csrc
|
||||
LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(abspath $(sim_dir)) -lfesvr -lpthread
|
||||
|
||||
|
||||
@ -62,8 +62,9 @@ CONFIGS=AMBAUnitTestConfig TLSimpleUnitTestConfig TLWidthUnitTestConfig
|
||||
endif
|
||||
|
||||
ifeq ($(SUITE), JtagDtmSuite)
|
||||
CONFIGS_32=WithJtagDTM_DefaultRV32Config
|
||||
CONFIGS_64=WithJtagDTM_DefaultConfig
|
||||
PROJECT=freechips.rocketchip.system
|
||||
CONFIGS_32=WithJtagDTMSystem_DefaultRV32Config
|
||||
CONFIGS_64=WithJtagDTMSystem_DefaultConfig
|
||||
CONFIGS += $(CONFIGS_32)
|
||||
CONFIGS += $(CONFIGS_64)
|
||||
endif
|
||||
@ -208,44 +209,87 @@ stamps/%/emulator-torture-$(TORTURE_CONFIG).stamp: stamps/%/emulator-debug.stamp
|
||||
|
||||
# Targets for JTAG DTM full-chain simulation
|
||||
|
||||
OPENOCD_DIR ?= $(RISCV)
|
||||
|
||||
# If this is defined empty, then all tests would run.
|
||||
JTAG_DTM_TEST ?= MemTest64
|
||||
GDBSERVER = $(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
|
||||
--print-failures \
|
||||
--print-log-names
|
||||
|
||||
ifdef DEBUG
|
||||
JTAG_STAMP_SUFFIX=-debug
|
||||
JTAG_DEBUG_SUFFIX=-debug
|
||||
JTAG_VCDPLUS_32= +vcdplusfile=regression32.vcd
|
||||
JTAG_VCDPLUS_64= +vcdplusfile=regression64.vcd
|
||||
VSIM_JTAG_VCDPLUS_32= +vcdplusfile=regression32.vcd
|
||||
VSIM_JTAG_VCDPLUS_64= +vcdplusfile=regression64.vcd
|
||||
EMULATOR_JTAG_VCDPLUS_32= -v regression32.vcd
|
||||
EMULATOR_JTAG_VCDPLUS_64= -v regression64.vcd
|
||||
OPENOCD_DEBUG= -d
|
||||
else
|
||||
JTAG_STAMP_SUFFIX=-ndebug
|
||||
endif
|
||||
|
||||
stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFFIX).stamp
|
||||
export RISCV=$(RISCV) && $(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
|
||||
--sim_cmd "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(JTAG_VCDPLUS_32)" \
|
||||
--server_cmd="$(OPENOCD_DIR)/bin/openocd $(OPENOCD_DEBUG) \
|
||||
--s $(OPENOCD_DIR)/share/openocd/scripts" \
|
||||
--freedom-e300-sim \
|
||||
ifdef SEED
|
||||
SEED_ARG = --seed $(SEED)
|
||||
endif
|
||||
|
||||
JTAG_DTM_SIM_ARGS = +verbose +jtag_rbb_enable=1 $(SEED_ARG)
|
||||
|
||||
stamps/riscv-tests.stamp:
|
||||
git -C $(abspath $(TOP)) submodule update --init riscv-tools
|
||||
git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-tests
|
||||
date > $@
|
||||
|
||||
stamps/%/vsim-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp
|
||||
RISCV=$(RISCV) $(GDBSERVER) \
|
||||
--sim_cmd="$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) $(JTAG_DTM_SIM_ARGS) $(VSIM_JTAG_VCDPLUS_32)" \
|
||||
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
|
||||
-s $(RISCV)/share/openocd/scripts" \
|
||||
--32 \
|
||||
$(abspath $(TOP))/scripts/RocketSim32.py \
|
||||
$(JTAG_DTM_TEST)
|
||||
date > $@
|
||||
|
||||
stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFFIX).stamp
|
||||
export RISCV=$(RISCV) && $(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
|
||||
--sim_cmd "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(JTAG_VCDPLUS_64)" \
|
||||
stamps/%/vsim-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp
|
||||
RISCV=$(RISCV) $(GDBSERVER) \
|
||||
--sim_cmd="$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) $(JTAG_DTM_SIM_ARGS) $(VSIM_JTAG_VCDPLUS_64)" \
|
||||
--server_cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd $(OPENOCD_DEBUG) \
|
||||
--s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
|
||||
--freedom-u500-sim \
|
||||
-s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
|
||||
--64 \
|
||||
$(abspath $(TOP))/scripts/RocketSim64.py \
|
||||
$(JTAG_DTM_TEST)
|
||||
date > $@
|
||||
|
||||
JTAG_DTM_32_TEST_STAMPS=$(foreach config,$(CONFIGS_32),stamps/$(config)/jtag-dtm-32-$(JTAG_DTM_TEST).stamp)
|
||||
JTAG_DTM_64_TEST_STAMPS=$(foreach config,$(CONFIGS_64),stamps/$(config)/jtag-dtm-64-$(JTAG_DTM_TEST).stamp)
|
||||
stamps/%/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp
|
||||
RISCV=$(RISCV) $(GDBSERVER) \
|
||||
--sim_cmd="$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) $(JTAG_DTM_SIM_ARGS) $(EMULATOR_JTAG_VCDPLUS_32) dummybin" \
|
||||
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
|
||||
-s $(RISCV)/share/openocd/scripts" \
|
||||
--32 \
|
||||
$(abspath $(TOP))/scripts/RocketSim32.py \
|
||||
$(JTAG_DTM_TEST)
|
||||
date > $@
|
||||
|
||||
jtag-dtm-tests-32 : $(JTAG_DTM_32_TEST_STAMPS)
|
||||
jtag-dtm-tests-64 : $(JTAG_DTM_64_TEST_STAMPS)
|
||||
stamps/%/emulator-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp
|
||||
RISCV=$(RISCV) $(GDBSERVER) \
|
||||
--sim_cmd="$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) $(JTAG_DTM_SIM_ARGS) $(EMULATOR_JTAG_VCDPLUS_64) dummybin" \
|
||||
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
|
||||
-s $(RISCV)/share/openocd/scripts" \
|
||||
--64 \
|
||||
$(abspath $(TOP))/scripts/RocketSim64.py \
|
||||
$(JTAG_DTM_TEST)
|
||||
date > $@
|
||||
|
||||
VSIM_JTAG_DTM_32_TEST_STAMPS=$(foreach config,$(CONFIGS_32),stamps/$(config)/vsim-jtag-dtm-32-$(JTAG_DTM_TEST).stamp)
|
||||
VSIM_JTAG_DTM_64_TEST_STAMPS=$(foreach config,$(CONFIGS_64),stamps/$(config)/vsim-jtag-dtm-64-$(JTAG_DTM_TEST).stamp)
|
||||
|
||||
EMULATOR_JTAG_DTM_32_TEST_STAMPS=$(foreach config,$(CONFIGS_32),stamps/$(config)/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp)
|
||||
EMULATOR_JTAG_DTM_64_TEST_STAMPS=$(foreach config,$(CONFIGS_64),stamps/$(config)/emulator-jtag-dtm-64-$(JTAG_DTM_TEST).stamp)
|
||||
|
||||
vsim-jtag-dtm-tests-32 : $(VSIM_JTAG_DTM_32_TEST_STAMPS)
|
||||
vsim-jtag-dtm-tests-64 : $(VSIM_JTAG_DTM_64_TEST_STAMPS)
|
||||
|
||||
emulator-jtag-dtm-tests-32 : $(EMULATOR_JTAG_DTM_32_TEST_STAMPS)
|
||||
emulator-jtag-dtm-tests-64 : $(EMULATOR_JTAG_DTM_64_TEST_STAMPS)
|
||||
|
||||
# Targets for JTAG DTM full-chain simulation
|
||||
jtag-dtm-regression: jtag-dtm-tests-32 jtag-dtm-tests-64
|
||||
vsim-jtag-dtm-regression: vsim-jtag-dtm-tests-32 vsim-jtag-dtm-tests-64
|
||||
emulator-jtag-dtm-regression: emulator-jtag-dtm-tests-32 emulator-jtag-dtm-tests-64
|
||||
|
||||
@ -1 +1 @@
|
||||
Subproject commit 09a1ffe5afb57673e0641a86cdb94347056c5c06
|
||||
Subproject commit 98682995dc4a1ab8777ff45ba673cf2658e54ae2
|
||||
19
scripts/RocketSim.cfg
Normal file
19
scripts/RocketSim.cfg
Normal file
@ -0,0 +1,19 @@
|
||||
adapter_khz 10000
|
||||
|
||||
interface remote_bitbang
|
||||
remote_bitbang_host localhost
|
||||
#$::env(REMOTE_BITBANG_HOST)
|
||||
remote_bitbang_port $::env(JTAG_VPI_PORT)
|
||||
|
||||
set _CHIPNAME riscv
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
|
||||
|
||||
riscv set_reset_timeout_sec 120
|
||||
riscv set_command_timeout_sec 120
|
||||
|
||||
init
|
||||
halt
|
||||
echo "Ready for Remote Connections"
|
||||
21
scripts/RocketSim.py
Normal file
21
scripts/RocketSim.py
Normal file
@ -0,0 +1,21 @@
|
||||
import targets
|
||||
import testlib
|
||||
|
||||
class RocketSimHart(targets.Hart):
|
||||
# This isn't generically true, but it's true enough for the Default*Configs in this code for now.
|
||||
# to get these tests to pass.
|
||||
ram = 0x80000000
|
||||
ram_size = 0x4000
|
||||
instruction_hardware_breakpoint_count = 2
|
||||
pass
|
||||
|
||||
class RocketSim(targets.Target):
|
||||
harts = [RocketSimHart()]
|
||||
timeout_sec = 6000
|
||||
server_timeout_sec = 60*60
|
||||
openocd_config_path = "RocketSim.cfg"
|
||||
|
||||
def create(self):
|
||||
print "STARTING A SIMULATION"
|
||||
print self.sim_cmd
|
||||
return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
|
||||
22
scripts/RocketSim32.py
Normal file
22
scripts/RocketSim32.py
Normal file
@ -0,0 +1,22 @@
|
||||
import targets
|
||||
import testlib
|
||||
|
||||
class RocketSimHart(targets.Hart):
|
||||
xlen = 32
|
||||
# This isn't generically true, but it's true enough for the Default*Configs in this code for now.
|
||||
# to get these tests to pass.
|
||||
ram = 0x80000000
|
||||
ram_size = 0x4000
|
||||
instruction_hardware_breakpoint_count = 2
|
||||
pass
|
||||
|
||||
class RocketSim(targets.Target):
|
||||
harts = [RocketSimHart()]
|
||||
timeout_sec = 6000
|
||||
server_timeout_sec = 60*60
|
||||
openocd_config_path = "RocketSim.cfg"
|
||||
|
||||
def create(self):
|
||||
print "STARTING A SIMULATION"
|
||||
print self.sim_cmd
|
||||
return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
|
||||
22
scripts/RocketSim64.py
Normal file
22
scripts/RocketSim64.py
Normal file
@ -0,0 +1,22 @@
|
||||
import targets
|
||||
import testlib
|
||||
|
||||
class RocketSimHart(targets.Hart):
|
||||
# This isn't generically true, but it's true enough for the Default*Configs in this code for now.
|
||||
# to get these tests to pass.
|
||||
xlen = 64
|
||||
ram = 0x80000000
|
||||
ram_size = 0x4000
|
||||
instruction_hardware_breakpoint_count = 2
|
||||
pass
|
||||
|
||||
class RocketSim(targets.Target):
|
||||
harts = [RocketSimHart()]
|
||||
timeout_sec = 6000
|
||||
server_timeout_sec = 60*60
|
||||
openocd_config_path = "RocketSim.cfg"
|
||||
|
||||
def create(self):
|
||||
print "STARTING A SIMULATION"
|
||||
print self.sim_cmd
|
||||
return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
|
||||
@ -49,7 +49,8 @@ trait HasPeripheryDebugBundle {
|
||||
val dtm = Module(new SimDTM).connect(c, r, d, out)
|
||||
}
|
||||
debug.systemjtag.foreach { sj =>
|
||||
val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
|
||||
//val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
|
||||
val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, sj.reset, c, r, out)
|
||||
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
|
||||
}
|
||||
debug.psd.foreach { _ <> psd }
|
||||
@ -112,6 +113,36 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
|
||||
}
|
||||
}
|
||||
|
||||
class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay))) {
|
||||
val io = new Bundle {
|
||||
val clock = Clock(INPUT)
|
||||
val reset = Bool(INPUT)
|
||||
val jtag = new JTAGIO(hasTRSTn = true)
|
||||
val enable = Bool(INPUT)
|
||||
val init_done = Bool(INPUT)
|
||||
val exit = UInt(OUTPUT, 32)
|
||||
}
|
||||
|
||||
def connect(dutio: JTAGIO, jtag_reset: Bool, tbclock: Clock, tbreset: Bool, tbsuccess: Bool) = {
|
||||
dutio <> io.jtag
|
||||
jtag_reset := tbreset
|
||||
|
||||
io.clock := tbclock
|
||||
io.reset := tbreset
|
||||
|
||||
io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
|
||||
io.init_done := ~tbreset
|
||||
|
||||
// Success is determined by the gdbserver
|
||||
// which is controlling this simulation.
|
||||
tbsuccess := io.exit === UInt(1)
|
||||
when (io.exit >= UInt(2)) {
|
||||
printf("*** FAILED *** (exit code = %d)\n", io.exit >> UInt(1))
|
||||
stop(1)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
class JTAGVPI(tckHalfPeriod: Int = 2, cmdDelay: Int = 2)(implicit val p: Parameters)
|
||||
extends BlackBox ( Map ("TCK_HALF_PERIOD" -> IntParam(tckHalfPeriod),
|
||||
"CMD_DELAY" -> IntParam(cmdDelay))) {
|
||||
|
||||
@ -9,6 +9,8 @@ import freechips.rocketchip.coreplex._
|
||||
import freechips.rocketchip.devices.debug.{IncludeJtagDTM, JtagDTMKey}
|
||||
import freechips.rocketchip.diplomacy._
|
||||
|
||||
class WithJtagDTMSystem extends freechips.rocketchip.coreplex.WithJtagDTM
|
||||
|
||||
class BaseConfig extends Config(new BaseCoreplexConfig().alter((site,here,up) => {
|
||||
// DTS descriptive parameters
|
||||
case DTSModel => "freechips,rocketchip-unknown"
|
||||
|
||||
@ -16,13 +16,15 @@ sim_vsrcs = \
|
||||
$(generated_dir)/$(long_name).behav_srams.v \
|
||||
$(base_dir)/vsrc/$(TB).v \
|
||||
$(base_dir)/vsrc/SimDTM.v \
|
||||
$(base_dir)/vsrc/SimJTAG.v \
|
||||
$(bb_vsrcs)
|
||||
|
||||
# C sources
|
||||
|
||||
sim_csrcs = \
|
||||
$(base_dir)/csrc/SimDTM.cc \
|
||||
$(base_dir)/csrc/jtag_vpi.c
|
||||
$(base_dir)/csrc/SimJTAG.cc \
|
||||
$(base_dir)/csrc/remote_bitbang.cc \
|
||||
|
||||
#--------------------------------------------------------------------
|
||||
# Build Verilog
|
||||
|
||||
@ -45,30 +45,37 @@ module AsyncResetReg (
|
||||
input clk,
|
||||
input rst);
|
||||
|
||||
`ifdef RANDOMIZE
|
||||
integer initvar;
|
||||
reg [31:0] _RAND;
|
||||
initial begin
|
||||
`ifndef verilator
|
||||
#0.002 begin end
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
`ifdef RANDOMIZE
|
||||
integer initvar;
|
||||
reg [31:0] _RAND;
|
||||
_RAND = {1{$random}};
|
||||
if (~rst) begin
|
||||
`endif
|
||||
if (rst) begin
|
||||
`ifdef verilator
|
||||
q = 1'b0;
|
||||
`endif
|
||||
end
|
||||
`ifdef RANDOMIZE
|
||||
`ifndef verilator
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
else begin
|
||||
#0.002 begin end
|
||||
q = _RAND[0];
|
||||
end
|
||||
`endif
|
||||
`endif
|
||||
`endif // `ifdef RANDOMIZE
|
||||
end
|
||||
`endif // `ifdef RANDOMIZE
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
|
||||
|
||||
if (rst) begin
|
||||
q <= 1'b0;
|
||||
end else if (en) begin
|
||||
q <= d;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule // AsyncResetReg
|
||||
|
||||
|
||||
79
vsrc/SimJTAG.v
Normal file
79
vsrc/SimJTAG.v
Normal file
@ -0,0 +1,79 @@
|
||||
// See LICENSE.SiFive for license details.
|
||||
|
||||
import "DPI-C" function int jtag_tick
|
||||
(
|
||||
output bit jtag_TCK,
|
||||
output bit jtag_TMS,
|
||||
output bit jtag_TDI,
|
||||
output bit jtag_TRSTn,
|
||||
|
||||
input bit jtag_TDO
|
||||
);
|
||||
|
||||
module SimJTAG #(
|
||||
parameter TICK_DELAY = 50
|
||||
)(
|
||||
|
||||
input clock,
|
||||
input reset,
|
||||
|
||||
input enable,
|
||||
input init_done,
|
||||
|
||||
output jtag_TCK,
|
||||
output jtag_TMS,
|
||||
output jtag_TDI,
|
||||
output jtag_TRSTn,
|
||||
|
||||
input jtag_TDO_data,
|
||||
input jtag_TDO_driven,
|
||||
|
||||
output [31:0] exit
|
||||
);
|
||||
|
||||
reg [31:0] tickCounterReg;
|
||||
wire [31:0] tickCounterNxt;
|
||||
|
||||
assign tickCounterNxt = (tickCounterReg == 0) ? TICK_DELAY : (tickCounterReg - 1);
|
||||
|
||||
bit r_reset;
|
||||
|
||||
wire [31:0] random_bits = $random;
|
||||
|
||||
wire #0.1 __jtag_TDO = jtag_TDO_driven ?
|
||||
jtag_TDO_data : random_bits[0];
|
||||
|
||||
bit __jtag_TCK;
|
||||
bit __jtag_TMS;
|
||||
bit __jtag_TDI;
|
||||
bit __jtag_TRSTn;
|
||||
int __exit;
|
||||
|
||||
assign #0.1 jtag_TCK = __jtag_TCK;
|
||||
assign #0.1 jtag_TMS = __jtag_TMS;
|
||||
assign #0.1 jtag_TDI = __jtag_TDI;
|
||||
assign #0.1 jtag_TRSTn = __jtag_TRSTn;
|
||||
|
||||
assign #0.1 exit = __exit;
|
||||
|
||||
always @(posedge clock) begin
|
||||
r_reset <= reset;
|
||||
if (reset || r_reset) begin
|
||||
__exit = 0;
|
||||
tickCounterReg <= TICK_DELAY;
|
||||
end else begin
|
||||
if (enable && init_done) begin
|
||||
tickCounterReg <= tickCounterNxt;
|
||||
if (tickCounterReg == 0) begin
|
||||
__exit = jtag_tick(
|
||||
__jtag_TCK,
|
||||
__jtag_TMS,
|
||||
__jtag_TDI,
|
||||
__jtag_TRSTn,
|
||||
__jtag_TDO);
|
||||
end
|
||||
end // if (enable && init_done)
|
||||
end // else: !if(reset || r_reset)
|
||||
end // always @ (posedge clock)
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user