PLIC: priority/threshold are really WARL (RWSPECIAL). Explain why.
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@ -169,7 +169,8 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
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}
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def priorityRegDesc(i: Int) = if (i > 0) {
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RegFieldDesc(s"priority_$i", s"Acting priority of interrupt source $i", reset=if (nPriorities > 0) None else Some(1))
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RegFieldDesc(s"priority_$i", s"Acting priority of interrupt source $i",
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reset=if (nPriorities > 0) None else Some(1), access=RegFieldAccessType.RWSPECIAL)
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} else {
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RegFieldDesc("reserved", "", reset=Some(0), access=RegFieldAccessType.R)
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}
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@ -180,7 +181,8 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
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}
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def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) RegField(32, x, priorityRegDesc(i)) else RegField.r(32, x, priorityRegDesc(i))
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val priorityRegFields = Seq(PLICConsts.priorityBase -> RegFieldGroup("priority", Some("Acting priorities of each interrupt source. 32 bits for each interrupt source."),
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val priorityRegFields = Seq(PLICConsts.priorityBase -> RegFieldGroup("priority",
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Some(s"Acting priorities of each interrupt source. Maximum legal value is ${nPriorities}. 32 bits for each interrupt source."),
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priority.zipWithIndex.map{case (p, i) => priorityRegField(p, i)}))
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val pendingRegFields = Seq(PLICConsts.pendingBase -> RegFieldGroup("pending", Some("Pending Bit Array. 1 Bit for each interrupt source."),
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pending.zipWithIndex.map{case (b, i) => RegField.r(1, b, pendingRegDesc(i))}))
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@ -226,7 +228,8 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
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g.complete := c
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}
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def thresholdRegDesc(i: Int) = RegFieldDesc(s"threshold_$i", s"Interrupt & claim threshold for target $i", reset=if (nPriorities > 0) None else Some(1))
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def thresholdRegDesc(i: Int) = RegFieldDesc(s"threshold_$i", s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.",
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reset=if (nPriorities > 0) None else Some(1), access=RegFieldAccessType.RWSPECIAL)
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def thresholdRegField(x: UInt, i: Int) = if (nPriorities > 0) RegField(32, x, thresholdRegDesc(i)) else RegField.r(32, x, thresholdRegDesc(i))
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val hartRegFields = Seq.tabulate(nHarts) { i =>
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