Merge pull request #992 from freechipsproject/test_mode_reset
reset_catch: Allow Test Mode Overrides
This commit is contained in:
commit
cbd65cd247
@ -1029,12 +1029,12 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici
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val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip
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// This comes from tlClk domain.
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val debugUnavail = Vec(getNComponents(), Bool()).asInput
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val psd = new PSDTestMode().asInput
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}
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dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl)
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dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive)
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dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, "dmactiveSync", io.psd)
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dmInner.module.io.debugUnavail := io.debugUnavail
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}
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}
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@ -1067,6 +1067,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
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val dmi = new ClockedDMIIO().flip
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val in = node.bundleIn
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val debugInterrupts = intnode.bundleOut
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val psd = new PSDTestMode().asInput
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}
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dmOuter.module.io.dmi <> io.dmi.dmi
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@ -1077,6 +1078,8 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
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dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive
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dmInner.module.io.debugUnavail := io.ctrl.debugUnavail
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dmInner.module.io.psd <> io.psd
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io.ctrl <> dmOuter.module.io.ctrl
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}
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@ -3,7 +3,7 @@
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package freechips.rocketchip.devices.debug
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import Chisel._
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import chisel3.core.{IntParam}
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import chisel3.core.{IntParam, Input, Output}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.coreplex.HasPeripheryBus
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import freechips.rocketchip.devices.tilelink._
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@ -15,7 +15,8 @@ import freechips.rocketchip.util._
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case object IncludeJtagDTM extends Field[Boolean](false)
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/** A wrapper bundle containing one of the two possible debug interfaces */
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class DebugIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
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class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with CanHavePSDTestModeIO {
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val clockeddmi = (!p(IncludeJtagDTM)).option(new ClockedDMIIO().flip)
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val systemjtag = (p(IncludeJtagDTM)).option(new SystemJTAGIO)
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val ndreset = Bool(OUTPUT)
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@ -38,7 +39,12 @@ trait HasPeripheryDebugBundle {
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val debug: DebugIO
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def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2) {
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def connectDebug(c: Clock,
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r: Bool,
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out: Bool,
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tckHalfPeriod: Int = 2,
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cmdDelay: Int = 2,
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psd: PSDTestMode = new PSDTestMode().fromBits(0.U)): Unit = {
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debug.clockeddmi.foreach { d =>
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val dtm = Module(new SimDTM).connect(c, r, d, out)
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}
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@ -46,9 +52,10 @@ trait HasPeripheryDebugBundle {
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val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
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sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
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}
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debug.psd.foreach { _ <> psd }
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}
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}
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}
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trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle {
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val outer: HasPeripheryDebug
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@ -57,6 +64,7 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD
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debug.clockeddmi.foreach { dbg => outer.debug.module.io.dmi <> dbg }
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val dtm = debug.systemjtag.map { sj =>
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val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleParams).nDMIAddrSize, p(JtagDTMKey)))
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dtm.io.jtag <> sj.jtag
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@ -67,7 +75,10 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD
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outer.debug.module.io.dmi.dmi <> dtm.io.dmi
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outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK
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outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch")
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val psd = debug.psd.getOrElse(Wire(new PSDTestMode).fromBits(0.U))
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outer.debug.module.io.psd <> psd
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outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd)
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dtm
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}
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19
src/main/scala/util/PSDTestMode.scala
Normal file
19
src/main/scala/util/PSDTestMode.scala
Normal file
@ -0,0 +1,19 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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import freechips.rocketchip.config._
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case object IncludePSDTest extends Field[Boolean](false)
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class PSDTestMode extends Bundle {
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val test_mode = Bool()
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val test_mode_reset = Bool()
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// TODO: Clocks?
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}
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trait CanHavePSDTestModeIO {
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implicit val p: Parameters
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val psd = p(IncludePSDTest).option(new PSDTestMode().asInput)
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}
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@ -11,27 +11,37 @@ import Chisel._
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class ResetCatchAndSync (sync: Int = 3) extends Module {
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override def desiredName = s"ResetCatchAndSync_d${sync}"
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val io = new Bundle {
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val sync_reset = Bool(OUTPUT)
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val psd = new PSDTestMode().asInput
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}
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io.sync_reset := ~AsyncResetSynchronizerShiftReg(Bool(true), sync)
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io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset,
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~AsyncResetSynchronizerShiftReg(Bool(true), sync))
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}
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object ResetCatchAndSync {
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def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None): Bool = {
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def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
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psd: Option[PSDTestMode] = None): Bool = {
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val catcher = Module (new ResetCatchAndSync(sync))
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if (name.isDefined) {catcher.suggestName(name.get)}
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catcher.clock := clk
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catcher.reset := rst
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catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0)))
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catcher.io.sync_reset
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}
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def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
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def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
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def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool =
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apply(clk, rst, sync, Some(name), Some(psd))
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def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool =
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apply(clk, rst, name = Some(name), psd = Some(psd))
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}
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