riscv/rocket-chip
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debug regression: until XLEN fix is merged into riscv-tests, have to explicitly state the XLEN

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This commit is contained in:
Megan Wachs 2017-11-15 16:05:36 -08:00
parent bd5fe5d22e
commit 3de9a04272
3 changed files with 48 additions and 4 deletions
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8
regression/Makefile
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@ -239,7 +239,7 @@ stamps/%/vsim-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
--s $(RISCV)/share/openocd/scripts" \
--32 \
$(abspath $(TOP))/scripts/RocketSim.py \
$(abspath $(TOP))/scripts/RocketSim32.py \
$(JTAG_DTM_TEST)
date > $@
@ -249,7 +249,7 @@ stamps/%/vsim-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
--server_cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd $(OPENOCD_DEBUG) \
--s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
--64 \
$(abspath $(TOP))/scripts/RocketSim.py \
$(abspath $(TOP))/scripts/RocketSim64.py \
$(JTAG_DTM_TEST)
date > $@
@ -259,7 +259,7 @@ stamps/%/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_S
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
--s $(RISCV)/share/openocd/scripts" \
--32 \
$(abspath $(TOP))/scripts/RocketSim.py \
$(abspath $(TOP))/scripts/RocketSim32.py \
$(JTAG_DTM_TEST)
date > $@
@ -269,7 +269,7 @@ stamps/%/emulator-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_S
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
--s $(RISCV)/share/openocd/scripts" \
--64 \
$(abspath $(TOP))/scripts/RocketSim.py \
$(abspath $(TOP))/scripts/RocketSim64.py \
$(JTAG_DTM_TEST)
date > $@

22
scripts/RocketSim32.py Normal file
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@ -0,0 +1,22 @@
import targets
import testlib
class RocketSimHart(targets.Hart):
xlen = 32
# This isn't generically true, but it's true enough for the Default*Configs in this code for now.
# to get these tests to pass.
ram = 0x80000000
ram_size = 0x4000
instruction_hardware_breakpoint_count = 2
pass
class RocketSim(targets.Target):
harts = [RocketSimHart()]
timeout_sec = 6000
server_timeout_sec = 60*60
openocd_config_path = "RocketSim.cfg"
def create(self):
print "STARTING A SIMULATION"
print self.sim_cmd
return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)

22
scripts/RocketSim64.py Normal file
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@ -0,0 +1,22 @@
import targets
import testlib
class RocketSimHart(targets.Hart):
# This isn't generically true, but it's true enough for the Default*Configs in this code for now.
# to get these tests to pass.
xlen = 64
ram = 0x80000000
ram_size = 0x4000
instruction_hardware_breakpoint_count = 2
pass
class RocketSim(targets.Target):
harts = [RocketSimHart()]
timeout_sec = 6000
server_timeout_sec = 60*60
openocd_config_path = "RocketSim.cfg"
def create(self):
print "STARTING A SIMULATION"
print self.sim_cmd
return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)