SimJTAG: fix verilog typo
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@ -63,7 +63,7 @@ module SimJTAG #(
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if (reset || r_reset) begin
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__exit = 0;
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tickCounterReg <= TICK_DELAY;
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init_done_sticky <= 1/b0;
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init_done_sticky <= 1'b0;
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end else begin
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init_done_sticky <= init_done | init_done_sticky;
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if (enable && init_done_sticky) begin
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