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Async Reg: Doesn't properly reset for Verilator.

This commit is contained in:
Megan Wachs 2017-12-01 17:43:01 -08:00
parent 9df3604007
commit a97add954a

View File

@ -45,30 +45,37 @@ module AsyncResetReg (
input clk,
input rst);
`ifdef RANDOMIZE
integer initvar;
reg [31:0] _RAND;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
`ifdef RANDOMIZE
integer initvar;
reg [31:0] _RAND;
_RAND = {1{$random}};
if (~rst) begin
`endif
if (rst) begin
`ifdef verilator
q = 1'b0;
`endif
end
`ifdef RANDOMIZE
`ifndef verilator
`endif
`ifdef RANDOMIZE_REG_INIT
else begin
#0.002 begin end
q = _RAND[0];
end
`endif
`endif
`endif // `ifdef RANDOMIZE
end
`endif // `ifdef RANDOMIZE
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else if (en) begin
q <= d;
end
end
endmodule // AsyncResetReg