Commit Graph
45 Commits
Author SHA1 Message Date
Megan Wachs 5d1e9b793a signal_bundles: add missing file 2017-09-22 13:55:55 -07:00
Megan Wachs 81e301f9f7 pinctrl: Create extendable Signal classes 2017-09-22 13:17:31 -07:00
Megan Wachs 38f537c438 device pins: Create classes that can be something other than a Pin subclass 2017-09-20 16:43:42 -07:00
Megan Wachs 6a13639cf3 SPI: Make it easier to build arbitrary bundles 2017-09-20 16:21:21 -07:00
Megan WachsandGitHub d5554bfe95 Merge pull request #37 from sifive/synchronizers
remove duplicate ResetCatchAndSync definition
2017-09-07 13:34:14 -07:00
Megan Wachs 97c3fcb4b6 shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate 2017-09-06 10:59:07 -07:00
Megan Wachs 4381e395af i2c/uart: Name the synchronizers 2017-09-05 18:40:22 -07:00
Megan Wachs 48222bcd2d gpio: Use Synchronizer for the inputs 2017-09-05 18:35:09 -07:00
Megan Wachs 1feaefe4c5 i2c, uart: Use Synchronizer primitives for the inputs 2017-09-05 18:32:37 -07:00
Megan Wachs c68d556768 ShiftRegInit: use the rocket-chip version since it is there now 2017-09-05 17:51:40 -07:00
Megan Wachs 7d07e3af0b regs: remove duplicate ShiftReg file which is now in rocket-chip 2017-09-05 17:33:32 -07:00
Megan Wachs acb8889382 remove duplicate ResetCatchAndSync definition 2017-08-24 18:12:36 -07:00
Megan WachsandGitHub 402017d34e Merge pull request #35 from sifive/spi-buffers
spi: put a request buffer infront of SPI
2017-08-20 16:47:01 -07:00
Megan Wachs 70c25846b8 spi: Make memory mapped interface depth a parameter 2017-08-20 12:39:38 -07:00
Megan Wachs aa6d911c26 Ports: Rename the 'fromXYZPort' to 'fromPort' since it's redundant 2017-07-25 08:36:28 -07:00
Megan Wachs 2139ab0d98 Merge remote-tracking branch 'origin/master' into typed_pad_ctrl 2017-07-25 07:05:22 -07:00
Megan Wachs 0a80d1987d Merge remote-tracking branch 'origin/master' into typed_pad_ctrl 2017-07-24 10:11:52 -07:00
Megan Wachs 2bad829e6e gpio: Add missing file 2017-07-20 14:53:34 -07:00
Megan Wachs 06f0d20742 Add missing cloneType methods to pin bundles 2017-07-20 11:36:31 -07:00
Megan Wachs 00086c26e6 i2c: Remove pluralization on the bundle name, i2c not i2cs 2017-07-20 10:53:44 -07:00
Megan Wachs ef4f2ed888 Remove pluralization on interface names. Require clocks and resets explicitly when necessary 2017-07-19 14:51:50 -07:00
Megan Wachs 4d74e8f67f Make it possible to adjust the type of pad controls used,
and seperate out some of the "GPIO Peripheral" from "Pin Control"
2017-07-19 08:01:42 -07:00
Megan WachsandGitHub 2154e9eb3f gpio: Make IOF optional (#21)
* gpio: Make IOF optional

* IOF: Make the default false
2017-06-19 12:41:38 -07:00
Megan Wachs 8bfda68858 More Peripheral-to-pins cleanups 2017-06-13 11:00:29 -07:00
Megan Wachs b3f656affe UART: actually return the pins, not just the module. We should do this for the other peripherals as well 2017-06-12 18:08:35 -07:00
Megan Wachs b06b80dccd GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful. 2017-06-12 17:53:51 -07:00
Megan Wachs 7c118790cb GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful. 2017-06-12 17:53:08 -07:00
Megan WachsandGitHub 27b00e177c Merge pull request #17 from sifive/peripheral_options
Make more peripherals "listable" to allow for 0 or more
2017-06-09 22:07:43 -07:00
Megan Wachs 79f64de12c peripheral_options: Actually compiles 2017-06-09 13:53:22 -07:00
Megan Wachs 29226701a8 SPIFlash: make it listable 2017-06-08 16:29:01 -07:00
Megan Wachs c89f163c0d GPIO: Make GPIO peripheral another listable one 2017-06-08 16:25:20 -07:00
Megan WachsandGitHub ebd3ffa57e Merge pull request #7 from sifive/ndreset
MockAON: Accept the non-debug interrupt as an input to overall reset.
2017-04-10 14:25:08 -07:00
Megan Wachs 9ba47b76c6 MockAON: Accept the non-debug interrupt as an input to overall reset. 2017-04-07 16:42:32 -07:00
Megan WachsandGitHub dbd16e305d Merge pull request #6 from sifive/debug_v013
Debug v013
2017-03-31 15:14:35 -07:00
Megan Wachs 70ac4044d1 spi: correct polarity of FIRRTL combo loop detection workaround. 2017-03-31 13:49:34 -07:00
Megan Wachs 1af6ce1c85 Merge remote-tracking branch 'origin/fix-false-comb-loop' into HEAD 2017-03-30 20:01:30 -07:00
Megan Wachs 3f6f10f4ed Merge remote-tracking branch 'origin/master' into debug-0.13 2017-03-27 18:48:24 -07:00
Megan Wachs faeb14dc5a JTAG: make TRSTn optional for all helpers as well to match the IO. 2017-03-24 17:27:55 -07:00
Megan Wachs 2c47cc4abd Merge remote-tracking branch 'origin/master' into debug-0.13 2017-03-22 19:16:20 -07:00
Megan Wachs c6d7326669 TLSPI: address parameter must now be a sequence. 2017-03-21 17:51:33 -07:00
Megan Wachs 77246eaada Adjust JTAG for rocket-chip changes 2017-03-14 14:52:39 -07:00
Megan Wachs 25356957fe Merge remote-tracking branch 'origin/master' into debug-0.13 2017-03-10 14:09:24 -08:00
Megan Wachs bf9b81f2bc jtag: The jtag interfaces have moved to a different package. 2017-03-02 14:46:34 -08:00
Megan WachsandGitHub 072d0c1b58 Merge pull request #2 from sifive/homogenous_bag_peripherals
Use HeterogenousBag to handle lists of peripherals
2017-02-16 18:45:48 -08:00
Megan Wachs 03be9aba67 Use HomogenousBag to handle lists of peripherals
Previously we had to do weird things to make non-homogenous
lists of items (e.g. PWM Peripherals where ncmp were different from one to
the other) into a vector. But now Chisel supports a Record type,
and we use the HomogenousBag utility to do this more naturally.
This also deletes all the cruft which was introduced to get
around the limitation which doesn't exist anymore.
2017-02-16 17:52:24 -08:00