riscv/rocket-chip
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  • a73aa351ca rocketchip: fix all clock crossings Wesley W. Terpstra 2016-10-27 15:34:37 -0700
  • 825c253a72 rocketchip: move TL2 and cake pattern into Coreplex Wesley W. Terpstra 2016-10-26 22:28:40 -0700
  • 89139a9492 Plic: split constants from variables used in config string Wesley W. Terpstra 2016-10-27 13:09:11 -0700
  • 11121b6f4c rocket: convert scratchpad to TL2 Wesley W. Terpstra 2016-10-26 19:54:47 -0700
  • dddb50a942 BuildTiles: convert to LazyTile Wesley W. Terpstra 2016-10-26 19:02:04 -0700
  • f8a0829134 rocketchip: remove clint; it moves into coreplex Wesley W. Terpstra 2016-10-26 17:48:15 -0700
  • 5090ff945b DebugModule: Be more paranoid about addressing corner cases. Megan Wachs 2016-10-26 18:03:07 -0700
  • b99662796d PLIC: converted to TL2 Wesley W. Terpstra 2016-10-26 13:52:23 -0700
  • bddfa4d69b Debug: make address configurable Wesley W. Terpstra 2016-10-26 13:27:35 -0700
  • c3dacca39a rocketchip: remove pbus; TL2 has swallowed it completely Wesley W. Terpstra 2016-10-25 18:18:06 -0700
  • 10d084b9f3 DebugModule: Use the power of RegisterRouter to simplify the DebugROM code. Megan Wachs 2016-10-26 11:23:52 -0700
  • 3df797fcab rocketchip: replace TL1 MMIO with an example of TL2 MMIO Wesley W. Terpstra 2016-10-25 16:27:42 -0700
  • 650f6fb23f diplomacy: add BlindNodes for use as external ports Wesley W. Terpstra 2016-10-25 18:04:26 -0700
  • 0edcd3304a diplomacy Nodes: leave flipping to the MixedNode implementation Wesley W. Terpstra 2016-10-25 17:47:32 -0700
  • 082f338432 diplomacy Nodes: remove useless indirection Wesley W. Terpstra 2016-10-25 17:42:00 -0700
  • ec2d23b8b7 rocketchip: Bundle-slices need access to the outer LazyModule Wesley W. Terpstra 2016-10-25 14:38:14 -0700
  • 0ae45d0f24 rocketchip: bundle (=> B) need not be delayed; Module is constructed later Wesley W. Terpstra 2016-10-25 14:28:52 -0700
  • 0dbda2f07d rocketchip: remove obsolete pDevices used during TL1=>2 migration Wesley W. Terpstra 2016-10-25 14:09:26 -0700
  • af924d8c51 DebugModule: Instantiate TL2 DebugModule in BaseCoreplex Megan Wachs 2016-10-24 19:01:32 -0700
  • d530ef7236 DebugModule: translate to TL2 with {32,64}-bit XLen width Megan Wachs 2016-10-24 18:13:23 -0700
  • 3e08d615f0 Merge pull request #427 from ucb-bar/put-after-release-bugfix Howard Mao 2016-10-31 11:28:24 -0700
  • f0e9a2a081 Fix PutBlock after Release bug Howard Mao 2016-10-28 18:23:50 -0700
  • cb81ea516c add regression test for put-after-release bug Howard Mao 2016-10-28 18:20:47 -0700
  • fa8844d5c3 properly use rocket MT_ constants in regression tests Howard Mao 2016-10-28 18:20:29 -0700
  • f8bb67ab8f Bind some Make vars early to avoid redundant evaluation Andrew Waterman 2016-10-28 11:56:13 -0700
  • f3c726033a Make all Chisel invocations depend on FIRRTL_JAR Andrew Waterman 2016-10-28 11:56:05 -0700
  • 2b65478f3a bump chisel/firrtl Andrew Waterman 2016-10-27 23:45:01 -0700
  • e45b41b4b6 Don't rely on SeqMem output after read-enable is low Andrew Waterman 2016-10-27 23:44:10 -0700
  • 190a8b9dd3 Update README.md to reflect firrtl and riscv-tools changes Andrew Waterman 2016-10-26 16:47:25 -0700
  • 8c538f548b Merge pull request #422 from ucb-bar/use-random-port-for-jtag-vpi Richard Xia 2016-10-26 13:16:28 -0700
  • cc5b7d1eb6 Bump riscv-tools. Richard Xia 2016-10-26 10:41:41 -0700
  • 183ae58704 Use a random port number for JTAG VPI. Richard Xia 2016-10-18 14:51:59 -0700
  • 900a7bbcf1 add PutAtomic support to width adapter Howard Mao 2016-10-24 13:07:00 -0700
  • 47887c40ac Merge pull request #421 from ucb-bar/fix_async_fifo Jacob Chang 2016-10-25 18:22:27 -0700
  • fc5eb7cc64 Fixed AsyncFifo with reset messaging Jacob Chang 2016-10-25 16:44:20 -0700
  • fd2d48acda lazy_module: If the user actually specifies a name, just use it without appending module name. Megan Wachs 2016-10-25 14:29:54 -0700
  • a807c922d0 diplomacy: take names from the outermost common node Wesley W. Terpstra 2016-10-14 16:32:39 -0700
  • fee67c4abf diplomacy: add methods to find {out,in}ner-most common node Wesley W. Terpstra 2016-10-14 16:18:57 -0700
  • 67ab27f5a5 diplomacy: guess the LazyModule name from the containing class Wesley W. Terpstra 2016-10-14 15:11:13 -0700
  • 4d50733548 tilelink2 ToAXI4: use helper method for a_last (#418) Wesley W. Terpstra 2016-10-25 10:16:42 -0700
  • 7dc97674d6 rocketchip: include an socBus between l1tol2 and periphery (#415) Wesley W. Terpstra 2016-10-24 23:56:09 -0700
  • a5ac106bb8 axi4 ToTL: fix decode error arbitration (#417) Wesley W. Terpstra 2016-10-24 22:15:19 -0700
  • 4c815f7958 tilelink2 Parameters: fix {contains,supports}Safe (#416) Wesley W. Terpstra 2016-10-24 20:37:04 -0700
  • b9a082223c Merge pull request #414 from ucb-bar/sanity-check-debug Scott Johnson 2016-10-24 15:58:29 -0700
  • f382ee70da Sanity check compile-time vs simulation-time options Scott Johnson 2016-10-24 14:45:34 -0700
  • 737cf82478 Print out seed if we can (#412) Colin Schmidt 2016-10-24 12:36:29 -0700
  • bc01f85164 Merge pull request #406 from ucb-bar/incisive-fixes Scott Johnson 2016-10-24 10:48:24 -0700
  • 9326cfd64a Merge branch 'master' into incisive-fixes Andrew Waterman 2016-10-23 23:08:01 -0700
  • 288d7169ae Bump firrtl and update vsim Makefrag-verilog (#409) Jack Koenig 2016-10-23 23:07:47 -0700
  • 8bfd6bcd4d axi4: ensure we accept AR before reporting R (#411) Wesley W. Terpstra 2016-10-21 21:02:05 -0700
  • cb8878c931 Don't build any hurricane branches Colin Schmidt 2016-10-14 16:38:10 -0700
  • 85f3788ab5 initialize s2_hit to solve #401 Colin Schmidt 2016-10-17 18:33:03 -0700
  • a919a280e8 Fix Cadence Incisive compile errors; VCD-Plus is a VCS-only format Scott Johnson 2016-10-19 13:11:18 -0700
  • 9f0fda01b3 Fix Cadence Incisive compile warning Scott Johnson 2016-10-19 13:18:17 -0700
  • f069052969 Merge pull request #403 from ucb-bar/fix-incisive-warning Scott Johnson 2016-10-18 10:48:32 -0700
  • dc4c375c7f Silence Verilog compile warning from Cadence Incisive Scott Johnson 2016-10-17 15:44:24 -0700
  • c8fc05d154 Merge pull request #402 from ucb-bar/axi4-slave Wesley W. Terpstra 2016-10-17 10:34:29 -0700
  • 7c334e3c34 axi4 ToTL: shorter critical path on Q.bits if errors go first Wesley W. Terpstra 2016-10-17 00:56:54 -0700
  • 73010c79a3 axi4 ToTL: handle bad AXI addresses Wesley W. Terpstra 2016-10-17 00:12:26 -0700
  • 501d6d689f axi4: Test ToTL Wesley W. Terpstra 2016-10-16 20:18:49 -0700
  • 5a1da63b5a axi4: prototype ToTL adapter Wesley W. Terpstra 2016-10-16 19:47:58 -0700
  • 72e5a97d40 tilelink2: factor out the OH1ToOH function Wesley W. Terpstra 2016-10-16 19:57:56 -0700
  • d09f43c32f axi4 Bundles: add a size calculation helper Wesley W. Terpstra 2016-10-16 21:59:39 -0700
  • ee66fd28eb Merge pull request #400 from ucb-bar/better-crossing-asserts Wesley W. Terpstra 2016-10-14 19:19:37 -0700
  • 20288729b9 tilelink2 Isolation: cross the valid signals as well Wesley W. Terpstra 2016-10-14 18:06:57 -0700
  • 680a944f07 regmapper RegisterCrossing: safe AsyncQueues are overkill here Wesley W. Terpstra 2016-10-14 18:06:24 -0700
  • ac0bb841da AsyncQueue: cope with far reset propagation delay Wesley W. Terpstra 2016-10-14 18:05:35 -0700
  • 8f3c2ddfc3 tilelink2 Crossing: these asserts should be done by the AsyncQueue Wesley W. Terpstra 2016-10-14 16:54:09 -0700
  • a82cfb8306 tilelink2: replace addr_hi with address (#397) Wesley W. Terpstra 2016-10-14 14:09:39 -0700
  • 9655621aa8 Merge pull request #396 from ucb-bar/decoupled Wesley W. Terpstra 2016-10-13 19:09:58 -0700
  • 4e40f9bb59 tilelink2 Nodes: appease the PC police Wesley W. Terpstra 2016-10-13 10:29:55 -0700
  • 54b73aef57 tilelink2: WidthWidget and Fragmenter no longer erase latency Wesley W. Terpstra 2016-10-12 21:11:32 -0700
  • 200cf3dd13 tilelink2 Nodes: include some options to test for conformance Wesley W. Terpstra 2016-10-12 21:02:31 -0700
  • 5d5b5a66f4 tilelink2 RAMModel: fix a write-bad-data bug Wesley W. Terpstra 2016-10-12 21:02:01 -0700
  • e5a1483358 tilelink2 Fragmenter: eliminate most of the registers on A Wesley W. Terpstra 2016-10-12 20:27:26 -0700
  • 99c7003d11 tilelink2: allow preemption of Fragmenter and WidthWidget Wesley W. Terpstra 2016-10-12 20:11:05 -0700
  • b42cfdc9dd tilelink2 Arbiter: there is only one winner Wesley W. Terpstra 2016-10-12 18:37:24 -0700
  • b6e9b0c558 tilelink2 Arbiter: allow preemption of first beat Wesley W. Terpstra 2016-10-12 18:35:16 -0700
  • 0aebf9e341 tilelink2 ToAXI4: no arbitration path register needed Wesley W. Terpstra 2016-10-12 18:11:09 -0700
  • 0e897b905f tilelink2 RegisterRouter: data path register is no longer required Wesley W. Terpstra 2016-10-12 18:10:07 -0700
  • c4eadd3ab3 tilelink2 Monitor: enforce stricter transaction ordering Wesley W. Terpstra 2016-10-12 18:55:57 -0700
  • d8a1163131 tilelink2 Monitor: don't enforce Irrevocable any more Wesley W. Terpstra 2016-10-12 18:09:38 -0700
  • 405f66da32 tilelink2 WidthWidget: cope with Decoupled inputs Wesley W. Terpstra 2016-10-12 18:47:01 -0700
  • e2e72ac979 tilelink2 Fragmenter: cope with Decoupled input Wesley W. Terpstra 2016-10-12 18:58:29 -0700
  • 023c6402e9 tilelink2: switch to DecoupledIO syntax Wesley W. Terpstra 2016-10-12 18:09:01 -0700
  • 980bb3fbfd Merge pull request #395 from ucb-bar/axi4-fragmenter Wesley W. Terpstra 2016-10-13 17:01:53 -0700
  • 4c1c52486b axi4 Fragmenter: handle more inflight AXI requests than we have space Wesley W. Terpstra 2016-10-13 15:25:21 -0700
  • 8005266131 axi4 Fragmenter: refine sideband FSM for case of last fragment Wesley W. Terpstra 2016-10-13 14:57:01 -0700
  • 19064e602b axi4 Fragmenter: align all output accesses Wesley W. Terpstra 2016-10-13 13:57:59 -0700
  • 84be93f9f3 axi4 Fragmenter: confirm correct handling of last Wesley W. Terpstra 2016-10-13 13:49:47 -0700
  • 1c79a23a8b axi4 Fragmenter: initialize error response to 0 Wesley W. Terpstra 2016-10-13 13:46:24 -0700
  • 958af132ba axi4 Fragmenter: optimize dynamic slave lookup Wesley W. Terpstra 2016-10-12 17:25:29 -0700
  • 11169d155c axi4: add a Buffer to put between nodes Wesley W. Terpstra 2016-10-11 22:49:54 -0700
  • a9a3f7dd4e tilelink2 RAMModel: include name of test in output Wesley W. Terpstra 2016-10-11 22:32:06 -0700
  • 345eefd81b axi4: include unit tests Wesley W. Terpstra 2016-10-11 22:27:01 -0700
  • a6c6d99848 axi4: prototype Fragmenter Wesley W. Terpstra 2016-10-11 22:36:40 -0700
  • c918aa6d89 axi4: name AdapterNode parameters properly Wesley W. Terpstra 2016-10-11 18:29:02 -0700
  • a423f97844 axi4: parameterized AXI master constraint for aligned access Wesley W. Terpstra 2016-10-10 11:47:40 -0700
  • 673cf1fdb5 tilelink2 ToAXI4: must create irrevocable D for now Wesley W. Terpstra 2016-10-12 14:13:26 -0700
  • 8e92ac32b7 tilelink2 ToAXI4: we need a Queue on B to guarantee deadlock freedom Wesley W. Terpstra 2016-10-11 22:26:04 -0700