riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

axi4: ensure we accept AR before reporting R (#411)

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-10-21 21:02:05 -07:00 committed by GitHub
parent cb8878c931
commit 8bfd6bcd4d
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/uncore/axi4/Fragmenter.scala
View File

@ -143,8 +143,8 @@ class AXI4Fragmenter(lite: Boolean = false, maxInFlight: Int = 32, combinational
val writeSizes1 = slaves.map(s => s.supportsWrite.max/beatBytes-1)
// Indirection variables for inputs and outputs; makes transformation application easier
val (in_ar, ar_last, _) = fragment(in.ar, readSizes1)
val (in_aw, aw_last, w_beats) = fragment(in.aw, writeSizes1)
val (in_ar, ar_last, _) = fragment(Queue.irrevocable(in.ar, 1, flow=true), readSizes1)
val (in_aw, aw_last, w_beats) = fragment(Queue.irrevocable(in.aw, 1, flow=true), writeSizes1)
val in_w = in.w
val in_r = in.r
val in_b = in.b