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Fix Cadence Incisive compile warning

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The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random
function) says: "The seed argument shall be an integral variable."

This fixes the following compile warning:

    rand_value = $random($urandom);
                       |
ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue.
This commit is contained in:
Scott Johnson 2016-10-19 13:18:17 -07:00
parent f069052969
commit 9f0fda01b3
1 changed files with 3 additions and 2 deletions
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5
vsrc/TestDriver.v
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@ -25,13 +25,14 @@ module TestDriver;
void'($value$plusargs("max-cycles=%d", max_cycles));
verbose = $test$plusargs("verbose");
// do not delete the line below.
// do not delete the lines below.
// $random function needs to be called with the seed once to affect all
// the downstream $random functions within the Chisel-generated Verilog
// code.
// $urandom is seeded via cmdline (+ntb_random_seed in VCS) but that
// doesn't seed $random.
rand_value = $random($urandom);
rand_value = $urandom;
rand_value = $random(rand_value);
if (verbose) begin
$fdisplay(stderr, "testing $random %0x", rand_value);
end