riscv/rocket-chip
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rocketchip: remove pbus; TL2 has swallowed it completely

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This commit is contained in:
Wesley W. Terpstra 2016-10-25 18:18:06 -07:00
parent 10d084b9f3
commit c3dacca39a
5 changed files with 7 additions and 12 deletions
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2
src/main/scala/coreplex/BaseCoreplex.scala
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@ -167,7 +167,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
for ((t, m) <- (uncoreTileIOs.map(_.slave).flatten) zip (tileSlavePorts map (cBus port _)))
t <> m
io.master.mmio <> cBus.port("pbus")
io.master.mmio <> cBus.port("TL2")
}
// Coreplex doesn't know when to stop running

2
src/main/scala/groundtest/Configs.scala
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@ -121,7 +121,7 @@ class WithComparator extends Config(
case BuildGroundTest =>
(p: Parameters) => Module(new ComparatorCore()(p))
case ComparatorKey => ComparatorParameters(
targets = Seq("mem", "io:pbus:TL2:testram").map(name =>
targets = Seq("mem", "io:TL2:testram").map(name =>
site(GlobalAddrMap)(name).start.longValue),
width = 8,
operations = 1000,

2
src/main/scala/groundtest/Regression.scala
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@ -71,7 +71,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
io.mem.grant.ready := Bool(true)
io.cache.req.valid := !get_sent && started
io.cache.req.bits.addr := UInt(addrMap("io:pbus:TL2:bootrom").start)
io.cache.req.bits.addr := UInt(addrMap("io:TL2:bootrom").start)
io.cache.req.bits.typ := MT_WU
io.cache.req.bits.cmd := M_XRD
io.cache.req.bits.tag := UInt(0)

6
src/main/scala/rocketchip/BaseTop.scala
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@ -80,11 +80,7 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](
val coreplex = p(BuildCoreplex)(outer.c, p)
val coreplexIO = Wire(coreplex.io)
val pBus =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:pbus"))(
p.alterPartial({ case TLId => "L2toMMIO" })))
pBus.io.in.head <> coreplexIO.master.mmio
outer.legacy.module.io.legacy <> pBus.port("TL2")
outer.legacy.module.io.legacy <> coreplexIO.master.mmio
println("Generated Address Map")
for (entry <- p(GlobalAddrMap).flatten) {

7
src/main/scala/rocketchip/Utils.scala
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@ -90,15 +90,14 @@ object GenerateGlobalAddrMap {
}).flatten.toList
lazy val tl2AddrMap = new AddrMap(uniquelyNamedTL2Devices, collapse = true)
lazy val pBusIOAddrMap = new AddrMap(Seq(AddrMapEntry("TL2", tl2AddrMap)), collapse = true)
val memBase = 0x80000000L
val memSize = p(ExtMemSize)
Dump("MEM_BASE", memBase)
val cBus = AddrMapEntry("cbus", cBusIOAddrMap)
val pBus = AddrMapEntry("pbus", pBusIOAddrMap)
val io = AddrMapEntry("io", AddrMap((cBus +: (!pBusIOAddrMap.isEmpty).option(pBus).toSeq):_*))
val tlBus = AddrMapEntry("TL2", tl2AddrMap)
val io = AddrMapEntry("io", AddrMap(cBus, tlBus))
val mem = AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))
AddrMap((io +: (p(NMemoryChannels) > 0).option(mem).toSeq):_*)
}
@ -108,7 +107,7 @@ object GenerateConfigString {
def apply(p: Parameters, c: CoreplexConfig, peripheryManagers: Seq[TLManagerParameters]) = {
val addrMap = p(GlobalAddrMap)
val plicAddr = addrMap("io:cbus:plic").start
val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:pbus:TL2:clint").start)
val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:TL2:clint").start)
val xLen = p(XLen)
val res = new StringBuilder
res append "plic {\n"