tilelink2 Fragmenter: cope with Decoupled input
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@ -190,8 +190,11 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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// Make the request Irrevocable
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val in_a = Queue(in.a, 1, flow=true)
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// If this is infront of a single manager, these become constants
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val find = manager.findFast(edgeIn.address(in.a.bits))
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val find = manager.findFast(edgeIn.address(in_a.bits))
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val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
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val maxLgLogical = Mux1H(find, maxLgLogicals)
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val maxLgGet = Mux1H(find, maxLgGets)
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@ -200,7 +203,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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val maxLgHint = Mux1H(find, maxLgHints)
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val limit = if (alwaysMin) lgMinSize else
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MuxLookup(in.a.bits.opcode, lgMinSize, Array(
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MuxLookup(in_a.bits.opcode, lgMinSize, Array(
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TLMessages.PutFullData -> maxLgPutFull,
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TLMessages.PutPartialData -> maxLgPutPartial,
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TLMessages.ArithmeticData -> maxLgArithmetic,
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@ -208,11 +211,11 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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TLMessages.Get -> maxLgGet,
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TLMessages.Hint -> maxLgHint))
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val aOrig = in.a.bits.size
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val aOrig = in_a.bits.size
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val aFrag = Mux(aOrig > limit, limit, aOrig)
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val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
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val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
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val aHasData = node.edgesIn(0).hasData(in.a.bits)
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val aHasData = node.edgesIn(0).hasData(in_a.bits)
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val aMask = Mux(aHasData, UInt(0), aFragOH1)
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val gennum = RegInit(UInt(0, width = counterBits))
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@ -224,11 +227,11 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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when (out.a.fire()) { gennum := new_gennum }
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val delay = !aHasData && aFragnum =/= UInt(0)
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out.a.valid := in.a.valid
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in.a.ready := out.a.ready && !delay
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out.a.bits := in.a.bits
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out.a.bits.addr_hi := in.a.bits.addr_hi | (~aFragnum << log2Ceil(minSize/beatBytes) & aOrigOH1 >> log2Ceil(beatBytes))
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out.a.bits.source := Cat(in.a.bits.source, aFragnum)
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out.a.valid := in_a.valid
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in_a.ready := out.a.ready && !delay
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out.a.bits := in_a.bits
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out.a.bits.addr_hi := in_a.bits.addr_hi | (~aFragnum << log2Ceil(minSize/beatBytes) & aOrigOH1 >> log2Ceil(beatBytes))
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out.a.bits.source := Cat(in_a.bits.source, aFragnum)
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out.a.bits.size := aFrag
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// Tie off unused channels
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