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tilelink2 RAMModel: fix a write-bad-data bug

This commit is contained in:
Wesley W. Terpstra 2016-10-12 21:02:01 -07:00
parent e5a1483358
commit 5d5b5a66f4
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/uncore/tilelink2/RAMModel.scala
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@ -103,7 +103,7 @@ class TLRAMModel(log: String = "") extends LazyModule
a_flight.size := edge.size(in.a.bits)
a_flight.opcode := in.a.bits.opcode
flight(in.a.bits.source) := a_flight
when (in.a.fire()) { flight(in.a.bits.source) := a_flight }
val bypass = if (edge.manager.minLatency > 0) Bool(false) else in.a.valid && in.a.bits.source === out.d.bits.source
val d_flight = RegNext(Mux(bypass, a_flight, flight(out.d.bits.source)))