riscv/rocket-chip
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rocketchip: remove obsolete pDevices used during TL1=>2 migration

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This commit is contained in:
Wesley W. Terpstra 2016-10-25 14:09:26 -07:00
parent af924d8c51
commit 0dbda2f07d
2 changed files with 5 additions and 13 deletions
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5
src/main/scala/rocketchip/BaseTop.scala
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@ -27,7 +27,6 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
// the following variables will be refactored properly with TL2
val pInterrupts = new RangeManager
val pBusMasters = new RangeManager
val pDevices = new ResourceManager[AddrMapEntry]
TLImp.emitMonitors = q(TLEmitMonitors)
@ -44,10 +43,10 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
hasSupervisor = q(UseVM)
)
lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, pDevices.get, peripheryManagers)
lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, peripheryManagers)
private val qWithMap = q.alterPartial({case GlobalAddrMap => genGlobalAddrMap})
lazy val genConfigString = GenerateConfigString(qWithMap, c, pDevices.get, peripheryManagers)
lazy val genConfigString = GenerateConfigString(qWithMap, c, peripheryManagers)
implicit val p = qWithMap.alterPartial({
case ConfigString => genConfigString
case NCoreplexExtClients => pBusMasters.sum})

13
src/main/scala/rocketchip/Utils.scala
View File

@ -53,7 +53,7 @@ class GlobalVariable[T] {
}
object GenerateGlobalAddrMap {
def apply(p: Parameters, pDevicesEntries: Seq[AddrMapEntry], peripheryManagers: Seq[TLManagerParameters]) = {
def apply(p: Parameters, peripheryManagers: Seq[TLManagerParameters]) = {
lazy val cBusIOAddrMap: AddrMap = {
val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
@ -90,7 +90,7 @@ object GenerateGlobalAddrMap {
}).flatten.toList
lazy val tl2AddrMap = new AddrMap(uniquelyNamedTL2Devices, collapse = true)
lazy val pBusIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: (p(ExtMMIOPorts) ++ pDevicesEntries), collapse = true)
lazy val pBusIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: p(ExtMMIOPorts), collapse = true)
val memBase = 0x80000000L
val memSize = p(ExtMemSize)
@ -105,7 +105,7 @@ object GenerateGlobalAddrMap {
}
object GenerateConfigString {
def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry], peripheryManagers: Seq[TLManagerParameters]) = {
def apply(p: Parameters, c: CoreplexConfig, peripheryManagers: Seq[TLManagerParameters]) = {
val addrMap = p(GlobalAddrMap)
val plicAddr = addrMap("io:cbus:plic").start
val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:pbus:TL2:clint").start)
@ -160,13 +160,6 @@ object GenerateConfigString {
res append " };\n"
}
res append "};\n"
pDevicesEntries foreach { entry =>
val region = addrMap("io:pbus:" + entry.name)
res append s"${entry.name} {\n"
res append s" addr 0x${region.start.toString(16)};\n"
res append s" size 0x${region.size.toString(16)}; \n"
res append "}\n"
}
peripheryManagers.foreach { manager => res append manager.dts }
res append '\u0000'
res.toString